69e26b4f43
For all cpuidle drivers that use CPUIDLE_FLAG_RCU_IDLE, ensure that all functions that call ct_cpuidle_enter() are marked __cpuidle. ( due to lack of noinstr validation on these platforms it is entirely possible this isn't complete ) Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20230112195542.274096325@infradead.org
119 lines
2.6 KiB
C
119 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* Copyright (C) 2014 Freescale Semiconductor, Inc.
|
|
*/
|
|
|
|
#include <linux/cpuidle.h>
|
|
#include <linux/cpu_pm.h>
|
|
#include <linux/module.h>
|
|
#include <asm/cacheflush.h>
|
|
#include <asm/cpuidle.h>
|
|
#include <asm/suspend.h>
|
|
|
|
#include "common.h"
|
|
#include "cpuidle.h"
|
|
#include "hardware.h"
|
|
|
|
static int imx6sx_idle_finish(unsigned long val)
|
|
{
|
|
/*
|
|
* for Cortex-A7 which has an internal L2
|
|
* cache, need to flush it before powering
|
|
* down ARM platform, since flushing L1 cache
|
|
* here again has very small overhead, compared
|
|
* to adding conditional code for L2 cache type,
|
|
* just call flush_cache_all() is fine.
|
|
*/
|
|
flush_cache_all();
|
|
cpu_do_idle();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static __cpuidle int imx6sx_enter_wait(struct cpuidle_device *dev,
|
|
struct cpuidle_driver *drv, int index)
|
|
{
|
|
imx6_set_lpm(WAIT_UNCLOCKED);
|
|
|
|
switch (index) {
|
|
case 1:
|
|
cpu_do_idle();
|
|
break;
|
|
case 2:
|
|
imx6_enable_rbc(true);
|
|
imx_gpc_set_arm_power_in_lpm(true);
|
|
imx_set_cpu_jump(0, v7_cpu_resume);
|
|
/* Need to notify there is a cpu pm operation. */
|
|
cpu_pm_enter();
|
|
cpu_cluster_pm_enter();
|
|
|
|
ct_cpuidle_enter();
|
|
cpu_suspend(0, imx6sx_idle_finish);
|
|
ct_cpuidle_exit();
|
|
|
|
cpu_cluster_pm_exit();
|
|
cpu_pm_exit();
|
|
imx_gpc_set_arm_power_in_lpm(false);
|
|
imx6_enable_rbc(false);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
imx6_set_lpm(WAIT_CLOCKED);
|
|
|
|
return index;
|
|
}
|
|
|
|
static struct cpuidle_driver imx6sx_cpuidle_driver = {
|
|
.name = "imx6sx_cpuidle",
|
|
.owner = THIS_MODULE,
|
|
.states = {
|
|
/* WFI */
|
|
ARM_CPUIDLE_WFI_STATE,
|
|
/* WAIT */
|
|
{
|
|
.exit_latency = 50,
|
|
.target_residency = 75,
|
|
.flags = CPUIDLE_FLAG_TIMER_STOP,
|
|
.enter = imx6sx_enter_wait,
|
|
.name = "WAIT",
|
|
.desc = "Clock off",
|
|
},
|
|
/* WAIT + ARM power off */
|
|
{
|
|
/*
|
|
* ARM gating 31us * 5 + RBC clear 65us
|
|
* and some margin for SW execution, here set it
|
|
* to 300us.
|
|
*/
|
|
.exit_latency = 300,
|
|
.target_residency = 500,
|
|
.flags = CPUIDLE_FLAG_TIMER_STOP |
|
|
CPUIDLE_FLAG_RCU_IDLE,
|
|
.enter = imx6sx_enter_wait,
|
|
.name = "LOW-POWER-IDLE",
|
|
.desc = "ARM power off",
|
|
},
|
|
},
|
|
.state_count = 3,
|
|
.safe_state_index = 0,
|
|
};
|
|
|
|
int __init imx6sx_cpuidle_init(void)
|
|
{
|
|
imx6_set_int_mem_clk_lpm(true);
|
|
imx6_enable_rbc(false);
|
|
imx_gpc_set_l2_mem_power_in_lpm(false);
|
|
/*
|
|
* set ARM power up/down timing to the fastest,
|
|
* sw2iso and sw can be set to one 32K cycle = 31us
|
|
* except for power up sw2iso which need to be
|
|
* larger than LDO ramp up time.
|
|
*/
|
|
imx_gpc_set_arm_power_up_timing(cpu_is_imx6sx() ? 0xf : 0x2, 1);
|
|
imx_gpc_set_arm_power_down_timing(1, 1);
|
|
|
|
return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
|
|
}
|