____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition Fixes: e112dc4e18ea ("iio: temperature: Add MAX31865 RTD Support") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Navin Sankar Velliangiri <navin@linumiz.com> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-92-jic23@kernel.org