23fbb5a87c
Fix EMAC soft reset on 460EX/GT to select the right PHY clock source before and after the soft reset. EMAC with PHY should use the clock from PHY during soft reset. EMAC without PHY should use the internal clock during soft reset. PPC460EX/GT Embedded Processor Advanced User's Manual section 28.10.1 Mode Register 0 (EMACx_MR0) states: Note: The PHY must provide a TX Clk in order to perform a soft reset of the EMAC. If none is present, select the internal clock (SDR0_ETH_CFG[EMACx_PHY_CLK] = 1). After a soft reset, select the external clock. Without the fix, 460EX/GT-based boards with RGMII PHYs attached to EMACs experience EMAC interrupt storm and system watchdog reset when issuing "ifconfig eth0 down" + "ifconfig eth0 up" a few times. The system enters endless loop of serving emac_irq() with EMACx_ISR register stuck at value 0x10000000 (Rx parity error). With the fix, the above issue is no longer observed. Signed-off-by: Petri Gynther <pgynther@google.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| ehea | ||
| emac | ||
| ibmveth.c | ||
| ibmveth.h | ||
| Kconfig | ||
| Makefile | ||