Swapnil Jakhade fa10517211 phy: cadence: Sierra: Add PHY PCS common register configurations
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Link: https://lore.kernel.org/r/20211223060137.9252-8-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27 16:35:09 +05:30
..
2021-02-09 09:32:35 +01:00
2021-06-23 10:33:34 +02:00