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- Support multiple ATU memory regions (Rob Herring)
- Warn if non-prefetchable memory aperture is > 32-bit (Vidya Sagar)
- Allow programming ATU for >4GB memory (Vidya Sagar)
- Move ATU offset out of driver match data (Rob Herring)
- Move "dbi", "dbi2", and "addr_space" resource setup to common code (Rob
Herring)
- Remove unneeded function wrappers (Rob Herring)
- Ensure all outbound ATU windows are reset to reduce dependencies on
bootloader (Rob Herring)
- Use the default MSI irq_chip for dra7xx (Rob Herring)
- Drop the .set_num_vectors() host op (Rob Herring)
- Move MSI interrupt setup into DWC common code (Rob Herring)
- Rework and simplify DWC MSI initialization (Rob Herring)
- Move link handling to DWC common code (Rob Herring)
- Move dw_pcie_msi_init() calls to DWC common code (Rob Herring)
- Move dw_pcie_setup_rc() calls to DWC common code (Rob Herring)
- Remove unnecessary wrappers around dw_pcie_host_init() (Rob Herring)
- Revert "keystone: Drop duplicated 'num-viewport'" to prepare for
detecting number of iATU regions without help from DT (Rob Herring)
- Move inbound and outbound windows to common struct (Rob Herring)
- Detect number of DWC iATU windows from device registers (Rob Herring)
- Drop samsung,exynos5440-pcie binding (Marek Szyprowski)
- Add samsung,exynos-pcie and samsung,exynos-pcie-phy bindings for
Exynos5433 variant (Marek Szyprowski)
- Rework phy-exynos-pcie driver to support Exynos5433 PCIe PHY (Jaehoon
Chung)
- Rework pci-exynos.c to support Exynos5433 PCIe host (Jaehoon Chung)
- Move tegra "dbi" accesses to post common DWC initialization (Vidya Sagar)
- Read tegra dbi" base address in application logic (Vidya Sagar)
- Fix tegra ASPM-L1SS advertisement disable code (Vidya Sagar)
- Set Tegra194 DesignWare IP version to 0x490A (Vidya Sagar)
- Continue tegra unconfig sequence even if parts fail (Vidya Sagar)
- Check return value of tegra_pcie_init_controller() (Vidya Sagar)
- Disable tegra LTSSM during L2 entry (Vidya Sagar)
- Add SM8250 SoC PCIe DT bindings and support (Manivannan Sadhasivam)
- Add SM8250 BDF to SID mapping (Manivannan Sadhasivam)
- Set 32-bit DMA mask for DWC MSI target address allocation (Vidya Sagar)
* remotes/lorenzo/pci/dwc:
PCI: dwc: Set 32-bit DMA mask for MSI target address allocation
PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
PCI: qcom: Add SM8250 SoC support
dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
PCI: tegra: Disable LTSSM during L2 entry
PCI: tegra: Check return value of tegra_pcie_init_controller()
PCI: tegra: Continue unconfig sequence even if parts fail
PCI: tegra: Set DesignWare IP version
PCI: tegra: Fix ASPM-L1SS advertisement disable code
PCI: tegra: Read "dbi" base address to program in application logic
PCI: tegra: Move "dbi" accesses to post common DWC initialization
PCI: dwc: exynos: Rework the driver to support Exynos5433 variant
phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding
dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding
dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding
PCI: dwc: Detect number of iATU windows
PCI: dwc: Move inbound and outbound windows to common struct
Revert "PCI: dwc/keystone: Drop duplicated 'num-viewport'"
PCI: dwc: Remove unnecessary wrappers around dw_pcie_host_init()
PCI: dwc: Move dw_pcie_setup_rc() to DWC common code
PCI: dwc: Move dw_pcie_msi_init() into core
PCI: dwc: Move link handling into common code
PCI: dwc: Rework MSI initialization
PCI: dwc: Move MSI interrupt setup into DWC common code
PCI: dwc: Drop the .set_num_vectors() host op
PCI: dwc/dra7xx: Use the common MSI irq_chip
PCI: dwc: Ensure all outbound ATU windows are reset
PCI: dwc/intel-gw: Remove some unneeded function wrappers
PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code
PCI: dwc/intel-gw: Move ATU offset out of driver match data
PCI: dwc: Add support to program ATU for >4GB memory
PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit
PCI: dwc: Support multiple ATU memory regions
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