Xiu Jianfeng bd72ab5e6f clk: socfpga: Fix memory leak in socfpga_gate_init() ...

[ Upstream commit 0b8ba891ad4d1ef6bfa4c72efc83f9f9f855f68b ]

Free @socfpga_clk and @ops on the error path to avoid memory leak issue.

Fixes: a30a67be7b6e ("clk: socfpga: Don't have get_parent for single parent ops")
Signed-off-by: Xiu Jianfeng <xiujianfeng@huawei.com>
Link: https://lore.kernel.org/r/20221123031622.63171-1-xiujianfeng@huawei.com
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

2022-12-31 13:32:26 +01:00

..

clk-agilex.c

clk: socfpga: agilex: Make use of the helper function devm_platform_ioremap_resource()

2022-01-05 16:43:41 -08:00

clk-gate-a10.c

clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return

2021-04-07 16:29:31 -07:00

clk-gate-s10.c

clk: cleanup comments

2022-03-11 18:22:15 -08:00

clk-gate.c

clk: socfpga: Fix memory leak in socfpga_gate_init()

2022-12-31 13:32:26 +01:00

clk-periph-a10.c

clk: socfpga: arria10: convert to use clk_hw

2021-03-30 19:26:26 -07:00

clk-periph-s10.c

clk: socfpga: cleanup spdx tags

2022-03-11 18:21:45 -08:00

clk-periph.c

clk: socfpga: use clk_hw_register for a5/c5

2021-03-30 19:26:26 -07:00

clk-pll-a10.c

clk: socfpga: arria10: convert to use clk_hw

2021-03-30 19:26:26 -07:00

clk-pll-s10.c

clk: socfpga: cleanup spdx tags

2022-03-11 18:21:45 -08:00

clk-pll.c

clk: socfpga: clk-pll: Remove unused variable 'rc'

2021-06-27 17:33:21 -07:00

clk-s10.c

clk: socfpga: cleanup spdx tags

2022-03-11 18:21:45 -08:00

clk.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13

2019-05-21 11:28:45 +02:00

clk.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288

2019-06-05 17:36:37 +02:00

Kconfig

clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)

2021-03-23 11:03:36 -05:00

Makefile

clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)

2021-03-23 11:03:36 -05:00

stratix10-clk.h

clk: agilex/stratix10: add support for the 2nd bypass

2021-06-27 16:39:59 -07:00