License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 17:07:57 +03:00
# SPDX-License-Identifier: GPL-2.0
2007-07-09 22:56:42 +04:00
#
# Generic algorithms support
#
config XOR_BLOCKS
tristate
2005-04-17 02:20:36 +04:00
#
async_tx: add the async_tx api
The async_tx api provides methods for describing a chain of asynchronous
bulk memory transfers/transforms with support for inter-transactional
dependencies. It is implemented as a dmaengine client that smooths over
the details of different hardware offload engine implementations. Code
that is written to the api can optimize for asynchronous operation and the
api will fit the chain of operations to the available offload resources.
I imagine that any piece of ADMA hardware would register with the
'async_*' subsystem, and a call to async_X would be routed as
appropriate, or be run in-line. - Neil Brown
async_tx exploits the capabilities of struct dma_async_tx_descriptor to
provide an api of the following general format:
struct dma_async_tx_descriptor *
async_<operation>(..., struct dma_async_tx_descriptor *depend_tx,
dma_async_tx_callback cb_fn, void *cb_param)
{
struct dma_chan *chan = async_tx_find_channel(depend_tx, <operation>);
struct dma_device *device = chan ? chan->device : NULL;
int int_en = cb_fn ? 1 : 0;
struct dma_async_tx_descriptor *tx = device ?
device->device_prep_dma_<operation>(chan, len, int_en) : NULL;
if (tx) { /* run <operation> asynchronously */
...
tx->tx_set_dest(addr, tx, index);
...
tx->tx_set_src(addr, tx, index);
...
async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
} else { /* run <operation> synchronously */
...
<operation>
...
async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
}
return tx;
}
async_tx_find_channel() returns a capable channel from its pool. The
channel pool is organized as a per-cpu array of channel pointers. The
async_tx_rebalance() routine is tasked with managing these arrays. In the
uniprocessor case async_tx_rebalance() tries to spread responsibility
evenly over channels of similar capabilities. For example if there are two
copy+xor channels, one will handle copy operations and the other will
handle xor. In the SMP case async_tx_rebalance() attempts to spread the
operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
channel0 while cpu1 gets copy channel 1 and xor channel 1. When a
dependency is specified async_tx_find_channel defaults to keeping the
operation on the same channel. A xor->copy->xor chain will stay on one
channel if it supports both operation types, otherwise the transaction will
transition between a copy and a xor resource.
Currently the raid5 implementation in the MD raid456 driver has been
converted to the async_tx api. A driver for the offload engines on the
Intel Xscale series of I/O processors, iop-adma, is provided in a later
commit. With the iop-adma driver and async_tx, raid456 is able to offload
copy, xor, and xor-zero-sum operations to hardware engines.
On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
improvement) and sequential reads to a degraded array (40 - 55%
improvement). For the other cases performance was roughly equal, +/- a few
percentage points. On a x86-smp platform the performance of the async_tx
implementation (in synchronous mode) was also +/- a few percentage points
of the original implementation. According to 'top' on iop342 CPU
utilization drops from ~50% to ~15% during a 'resync' while the speed
according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.
The tiobench command line used for testing was: tiobench --size 2048
--block 4096 --block 131072 --dir /mnt/raid --numruns 5
* iop342 had 1GB of memory available
Details:
* if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
async_tx_find_channel a static inline routine that always returns NULL
* when a callback is specified for a given transaction an interrupt will
fire at operation completion time and the callback will occur in a
tasklet. if the the channel does not support interrupts then a live
polling wait will be performed
* the api is written as a dmaengine client that requests all available
channels
* In support of dependencies the api implicitly schedules channel-switch
interrupts. The interrupt triggers the cleanup tasklet which causes
pending operations to be scheduled on the next channel
* Xor engines treat an xor destination address differently than a software
xor routine. To the software routine the destination address is an implied
source, whereas engines treat it as a write-only destination. This patch
modifies the xor_blocks routine to take a an explicit destination address
to mirror the hardware.
Changelog:
* fixed a leftover debug print
* don't allow callbacks in async_interrupt_cond
* fixed xor_block changes
* fixed usage of ASYNC_TX_XOR_DROP_DEST
* drop dma mapping methods, suggested by Chris Leech
* printk warning fixups from Andrew Morton
* don't use inline in C files, Adrian Bunk
* select the API when MD is enabled
* BUG_ON xor source counts <= 1
* implicitly handle hardware concerns like channel switching and
interrupts, Neil Brown
* remove the per operation type list, and distribute operation capabilities
evenly amongst the available channels
* simplify async_tx_find_channel to optimize the fast path
* introduce the channel_table_initialized flag to prevent early calls to
the api
* reorganize the code to mimic crypto
* include mm.h as not all archs include it in dma-mapping.h
* make the Kconfig options non-user visible, Adrian Bunk
* move async_tx under crypto since it is meant as 'core' functionality, and
the two may share algorithms in the future
* move large inline functions into c files
* checkpatch.pl fixes
* gpl v2 only correction
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-By: NeilBrown <neilb@suse.de>
2007-01-02 21:10:44 +03:00
# async_tx api: hardware offloaded memory transfer/transform support
2005-04-17 02:20:36 +04:00
#
async_tx: add the async_tx api
The async_tx api provides methods for describing a chain of asynchronous
bulk memory transfers/transforms with support for inter-transactional
dependencies. It is implemented as a dmaengine client that smooths over
the details of different hardware offload engine implementations. Code
that is written to the api can optimize for asynchronous operation and the
api will fit the chain of operations to the available offload resources.
I imagine that any piece of ADMA hardware would register with the
'async_*' subsystem, and a call to async_X would be routed as
appropriate, or be run in-line. - Neil Brown
async_tx exploits the capabilities of struct dma_async_tx_descriptor to
provide an api of the following general format:
struct dma_async_tx_descriptor *
async_<operation>(..., struct dma_async_tx_descriptor *depend_tx,
dma_async_tx_callback cb_fn, void *cb_param)
{
struct dma_chan *chan = async_tx_find_channel(depend_tx, <operation>);
struct dma_device *device = chan ? chan->device : NULL;
int int_en = cb_fn ? 1 : 0;
struct dma_async_tx_descriptor *tx = device ?
device->device_prep_dma_<operation>(chan, len, int_en) : NULL;
if (tx) { /* run <operation> asynchronously */
...
tx->tx_set_dest(addr, tx, index);
...
tx->tx_set_src(addr, tx, index);
...
async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
} else { /* run <operation> synchronously */
...
<operation>
...
async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
}
return tx;
}
async_tx_find_channel() returns a capable channel from its pool. The
channel pool is organized as a per-cpu array of channel pointers. The
async_tx_rebalance() routine is tasked with managing these arrays. In the
uniprocessor case async_tx_rebalance() tries to spread responsibility
evenly over channels of similar capabilities. For example if there are two
copy+xor channels, one will handle copy operations and the other will
handle xor. In the SMP case async_tx_rebalance() attempts to spread the
operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
channel0 while cpu1 gets copy channel 1 and xor channel 1. When a
dependency is specified async_tx_find_channel defaults to keeping the
operation on the same channel. A xor->copy->xor chain will stay on one
channel if it supports both operation types, otherwise the transaction will
transition between a copy and a xor resource.
Currently the raid5 implementation in the MD raid456 driver has been
converted to the async_tx api. A driver for the offload engines on the
Intel Xscale series of I/O processors, iop-adma, is provided in a later
commit. With the iop-adma driver and async_tx, raid456 is able to offload
copy, xor, and xor-zero-sum operations to hardware engines.
On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
improvement) and sequential reads to a degraded array (40 - 55%
improvement). For the other cases performance was roughly equal, +/- a few
percentage points. On a x86-smp platform the performance of the async_tx
implementation (in synchronous mode) was also +/- a few percentage points
of the original implementation. According to 'top' on iop342 CPU
utilization drops from ~50% to ~15% during a 'resync' while the speed
according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.
The tiobench command line used for testing was: tiobench --size 2048
--block 4096 --block 131072 --dir /mnt/raid --numruns 5
* iop342 had 1GB of memory available
Details:
* if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
async_tx_find_channel a static inline routine that always returns NULL
* when a callback is specified for a given transaction an interrupt will
fire at operation completion time and the callback will occur in a
tasklet. if the the channel does not support interrupts then a live
polling wait will be performed
* the api is written as a dmaengine client that requests all available
channels
* In support of dependencies the api implicitly schedules channel-switch
interrupts. The interrupt triggers the cleanup tasklet which causes
pending operations to be scheduled on the next channel
* Xor engines treat an xor destination address differently than a software
xor routine. To the software routine the destination address is an implied
source, whereas engines treat it as a write-only destination. This patch
modifies the xor_blocks routine to take a an explicit destination address
to mirror the hardware.
Changelog:
* fixed a leftover debug print
* don't allow callbacks in async_interrupt_cond
* fixed xor_block changes
* fixed usage of ASYNC_TX_XOR_DROP_DEST
* drop dma mapping methods, suggested by Chris Leech
* printk warning fixups from Andrew Morton
* don't use inline in C files, Adrian Bunk
* select the API when MD is enabled
* BUG_ON xor source counts <= 1
* implicitly handle hardware concerns like channel switching and
interrupts, Neil Brown
* remove the per operation type list, and distribute operation capabilities
evenly amongst the available channels
* simplify async_tx_find_channel to optimize the fast path
* introduce the channel_table_initialized flag to prevent early calls to
the api
* reorganize the code to mimic crypto
* include mm.h as not all archs include it in dma-mapping.h
* make the Kconfig options non-user visible, Adrian Bunk
* move async_tx under crypto since it is meant as 'core' functionality, and
the two may share algorithms in the future
* move large inline functions into c files
* checkpatch.pl fixes
* gpl v2 only correction
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-By: NeilBrown <neilb@suse.de>
2007-01-02 21:10:44 +03:00
source "crypto/async_tx/Kconfig"
2005-04-17 02:20:36 +04:00
async_tx: add the async_tx api
The async_tx api provides methods for describing a chain of asynchronous
bulk memory transfers/transforms with support for inter-transactional
dependencies. It is implemented as a dmaengine client that smooths over
the details of different hardware offload engine implementations. Code
that is written to the api can optimize for asynchronous operation and the
api will fit the chain of operations to the available offload resources.
I imagine that any piece of ADMA hardware would register with the
'async_*' subsystem, and a call to async_X would be routed as
appropriate, or be run in-line. - Neil Brown
async_tx exploits the capabilities of struct dma_async_tx_descriptor to
provide an api of the following general format:
struct dma_async_tx_descriptor *
async_<operation>(..., struct dma_async_tx_descriptor *depend_tx,
dma_async_tx_callback cb_fn, void *cb_param)
{
struct dma_chan *chan = async_tx_find_channel(depend_tx, <operation>);
struct dma_device *device = chan ? chan->device : NULL;
int int_en = cb_fn ? 1 : 0;
struct dma_async_tx_descriptor *tx = device ?
device->device_prep_dma_<operation>(chan, len, int_en) : NULL;
if (tx) { /* run <operation> asynchronously */
...
tx->tx_set_dest(addr, tx, index);
...
tx->tx_set_src(addr, tx, index);
...
async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
} else { /* run <operation> synchronously */
...
<operation>
...
async_tx_sync_epilog(flags, depend_tx, cb_fn, cb_param);
}
return tx;
}
async_tx_find_channel() returns a capable channel from its pool. The
channel pool is organized as a per-cpu array of channel pointers. The
async_tx_rebalance() routine is tasked with managing these arrays. In the
uniprocessor case async_tx_rebalance() tries to spread responsibility
evenly over channels of similar capabilities. For example if there are two
copy+xor channels, one will handle copy operations and the other will
handle xor. In the SMP case async_tx_rebalance() attempts to spread the
operations evenly over the cpus, e.g. cpu0 gets copy channel0 and xor
channel0 while cpu1 gets copy channel 1 and xor channel 1. When a
dependency is specified async_tx_find_channel defaults to keeping the
operation on the same channel. A xor->copy->xor chain will stay on one
channel if it supports both operation types, otherwise the transaction will
transition between a copy and a xor resource.
Currently the raid5 implementation in the MD raid456 driver has been
converted to the async_tx api. A driver for the offload engines on the
Intel Xscale series of I/O processors, iop-adma, is provided in a later
commit. With the iop-adma driver and async_tx, raid456 is able to offload
copy, xor, and xor-zero-sum operations to hardware engines.
On iop342 tiobench showed higher throughput for sequential writes (20 - 30%
improvement) and sequential reads to a degraded array (40 - 55%
improvement). For the other cases performance was roughly equal, +/- a few
percentage points. On a x86-smp platform the performance of the async_tx
implementation (in synchronous mode) was also +/- a few percentage points
of the original implementation. According to 'top' on iop342 CPU
utilization drops from ~50% to ~15% during a 'resync' while the speed
according to /proc/mdstat doubles from ~25 MB/s to ~50 MB/s.
The tiobench command line used for testing was: tiobench --size 2048
--block 4096 --block 131072 --dir /mnt/raid --numruns 5
* iop342 had 1GB of memory available
Details:
* if CONFIG_DMA_ENGINE=n the asynchronous path is compiled away by making
async_tx_find_channel a static inline routine that always returns NULL
* when a callback is specified for a given transaction an interrupt will
fire at operation completion time and the callback will occur in a
tasklet. if the the channel does not support interrupts then a live
polling wait will be performed
* the api is written as a dmaengine client that requests all available
channels
* In support of dependencies the api implicitly schedules channel-switch
interrupts. The interrupt triggers the cleanup tasklet which causes
pending operations to be scheduled on the next channel
* Xor engines treat an xor destination address differently than a software
xor routine. To the software routine the destination address is an implied
source, whereas engines treat it as a write-only destination. This patch
modifies the xor_blocks routine to take a an explicit destination address
to mirror the hardware.
Changelog:
* fixed a leftover debug print
* don't allow callbacks in async_interrupt_cond
* fixed xor_block changes
* fixed usage of ASYNC_TX_XOR_DROP_DEST
* drop dma mapping methods, suggested by Chris Leech
* printk warning fixups from Andrew Morton
* don't use inline in C files, Adrian Bunk
* select the API when MD is enabled
* BUG_ON xor source counts <= 1
* implicitly handle hardware concerns like channel switching and
interrupts, Neil Brown
* remove the per operation type list, and distribute operation capabilities
evenly amongst the available channels
* simplify async_tx_find_channel to optimize the fast path
* introduce the channel_table_initialized flag to prevent early calls to
the api
* reorganize the code to mimic crypto
* include mm.h as not all archs include it in dma-mapping.h
* make the Kconfig options non-user visible, Adrian Bunk
* move async_tx under crypto since it is meant as 'core' functionality, and
the two may share algorithms in the future
* move large inline functions into c files
* checkpatch.pl fixes
* gpl v2 only correction
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-By: NeilBrown <neilb@suse.de>
2007-01-02 21:10:44 +03:00
#
# Cryptographic API Configuration
#
2007-05-18 09:11:01 +04:00
menuconfig CRYPTO
2008-03-30 12:36:09 +04:00
tristate "Cryptographic API"
2022-07-25 21:36:34 +03:00
select CRYPTO_LIB_UTILS
2005-04-17 02:20:36 +04:00
help
This option provides the core Cryptographic API.
2006-08-21 15:08:13 +04:00
if CRYPTO
2008-04-05 17:04:48 +04:00
comment "Crypto core or helper"
2008-08-05 10:13:08 +04:00
config CRYPTO_FIPS
bool "FIPS 200 compliance"
2014-07-04 18:15:08 +04:00
depends on (CRYPTO_ANSI_CPRNG || CRYPTO_DRBG) && !CRYPTO_MANAGER_DISABLE_TESTS
2016-10-05 01:34:30 +03:00
depends on (MODULE_SIG || !MODULES)
2008-08-05 10:13:08 +04:00
help
2019-03-20 13:41:03 +03:00
This option enables the fips boot option which is
required if you want the system to operate in a FIPS 200
2008-08-05 10:13:08 +04:00
certification. You should say no unless you know what
2010-09-03 15:17:49 +04:00
this is.
2008-08-05 10:13:08 +04:00
2022-07-08 15:33:13 +03:00
config CRYPTO_FIPS_NAME
string "FIPS Module Name"
default "Linux Kernel Cryptographic API"
depends on CRYPTO_FIPS
help
This option sets the FIPS Module name reported by the Crypto API via
the /proc/sys/crypto/fips_name file.
config CRYPTO_FIPS_CUSTOM_VERSION
bool "Use Custom FIPS Module Version"
depends on CRYPTO_FIPS
default n
config CRYPTO_FIPS_VERSION
string "FIPS Module Version"
default "(none)"
depends on CRYPTO_FIPS_CUSTOM_VERSION
help
This option provides the ability to override the FIPS Module Version.
By default the KERNELRELEASE value is used.
2006-08-21 15:08:13 +04:00
config CRYPTO_ALGAPI
tristate
2008-12-10 15:29:44 +03:00
select CRYPTO_ALGAPI2
2006-08-21 15:08:13 +04:00
help
This option provides the API for cryptographic algorithms.
2008-12-10 15:29:44 +03:00
config CRYPTO_ALGAPI2
tristate
2007-08-30 11:36:14 +04:00
config CRYPTO_AEAD
tristate
2008-12-10 15:29:44 +03:00
select CRYPTO_AEAD2
2007-08-30 11:36:14 +04:00
select CRYPTO_ALGAPI
2008-12-10 15:29:44 +03:00
config CRYPTO_AEAD2
tristate
select CRYPTO_ALGAPI2
2015-08-13 12:28:58 +03:00
select CRYPTO_NULL2
select CRYPTO_RNG2
2008-12-10 15:29:44 +03:00
2019-10-25 22:41:13 +03:00
config CRYPTO_SKCIPHER
2006-08-21 18:07:53 +04:00
tristate
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER2
2006-08-21 18:07:53 +04:00
select CRYPTO_ALGAPI
2008-12-10 15:29:44 +03:00
2019-10-25 22:41:13 +03:00
config CRYPTO_SKCIPHER2
2008-12-10 15:29:44 +03:00
tristate
select CRYPTO_ALGAPI2
select CRYPTO_RNG2
2006-08-21 18:07:53 +04:00
2006-08-19 16:24:23 +04:00
config CRYPTO_HASH
tristate
2008-12-10 15:29:44 +03:00
select CRYPTO_HASH2
2006-08-19 16:24:23 +04:00
select CRYPTO_ALGAPI
2008-12-10 15:29:44 +03:00
config CRYPTO_HASH2
tristate
select CRYPTO_ALGAPI2
2008-08-14 16:15:52 +04:00
config CRYPTO_RNG
tristate
2008-12-10 15:29:44 +03:00
select CRYPTO_RNG2
2008-08-14 16:15:52 +04:00
select CRYPTO_ALGAPI
2008-12-10 15:29:44 +03:00
config CRYPTO_RNG2
tristate
select CRYPTO_ALGAPI2
2015-06-03 09:49:31 +03:00
config CRYPTO_RNG_DEFAULT
tristate
select CRYPTO_DRBG_MENU
2015-06-16 20:30:55 +03:00
config CRYPTO_AKCIPHER2
tristate
select CRYPTO_ALGAPI2
config CRYPTO_AKCIPHER
tristate
select CRYPTO_AKCIPHER2
select CRYPTO_ALGAPI
2016-06-22 19:49:13 +03:00
config CRYPTO_KPP2
tristate
select CRYPTO_ALGAPI2
config CRYPTO_KPP
tristate
select CRYPTO_ALGAPI
select CRYPTO_KPP2
2016-10-21 15:19:47 +03:00
config CRYPTO_ACOMP2
tristate
select CRYPTO_ALGAPI2
2018-01-05 19:26:47 +03:00
select SGL_ALLOC
2016-10-21 15:19:47 +03:00
config CRYPTO_ACOMP
tristate
select CRYPTO_ALGAPI
select CRYPTO_ACOMP2
2006-09-21 05:31:44 +04:00
config CRYPTO_MANAGER
tristate "Cryptographic algorithm manager"
2008-12-10 15:29:44 +03:00
select CRYPTO_MANAGER2
2006-09-21 05:31:44 +04:00
help
Create default cryptographic template instantiations such as
cbc(aes).
2008-12-10 15:29:44 +03:00
config CRYPTO_MANAGER2
def_tristate CRYPTO_MANAGER || (CRYPTO_MANAGER!=n && CRYPTO_ALGAPI=y)
select CRYPTO_AEAD2
select CRYPTO_HASH2
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER2
2015-06-16 20:31:06 +03:00
select CRYPTO_AKCIPHER2
2016-06-22 19:49:13 +03:00
select CRYPTO_KPP2
2016-10-21 15:19:47 +03:00
select CRYPTO_ACOMP2
2008-12-10 15:29:44 +03:00
2011-09-27 09:23:50 +04:00
config CRYPTO_USER
tristate "Userspace cryptographic algorithm configuration"
2011-11-01 05:12:43 +04:00
depends on NET
2011-09-27 09:23:50 +04:00
select CRYPTO_MANAGER
help
2011-11-09 10:29:20 +04:00
Userspace configuration for cryptographic instantiations such as
2011-09-27 09:23:50 +04:00
cbc(aes).
2010-08-06 05:40:28 +04:00
config CRYPTO_MANAGER_DISABLE_TESTS
bool "Disable run-time self tests"
2010-08-06 06:34:00 +04:00
default y
2010-06-03 14:53:43 +04:00
help
2010-08-06 05:40:28 +04:00
Disable run-time self tests that normally take place at
algorithm registration.
2010-06-03 14:53:43 +04:00
2019-02-01 10:51:44 +03:00
config CRYPTO_MANAGER_EXTRA_TESTS
bool "Enable extra run-time crypto self tests"
2020-11-02 16:48:15 +03:00
depends on DEBUG_KERNEL && !CRYPTO_MANAGER_DISABLE_TESTS && CRYPTO_MANAGER
2019-02-01 10:51:44 +03:00
help
Enable extra run-time self tests of registered crypto algorithms,
including randomized fuzz tests.
This is intended for developer use only, as these tests take much
longer to run than the normal self tests.
2008-04-05 17:04:48 +04:00
config CRYPTO_GF128MUL
2019-05-20 19:53:43 +03:00
tristate
2006-10-28 07:15:24 +04:00
2005-04-17 02:20:36 +04:00
config CRYPTO_NULL
tristate "Null algorithms"
2015-08-13 12:28:58 +03:00
select CRYPTO_NULL2
2005-04-17 02:20:36 +04:00
help
These are 'Null' algorithms, used by IPsec, which do nothing.
2015-08-13 12:28:58 +03:00
config CRYPTO_NULL2
2015-08-17 15:39:40 +03:00
tristate
2015-08-13 12:28:58 +03:00
select CRYPTO_ALGAPI2
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER2
2015-08-13 12:28:58 +03:00
select CRYPTO_HASH2
2010-01-07 07:57:19 +03:00
config CRYPTO_PCRYPT
2012-10-02 22:16:49 +04:00
tristate "Parallel crypto engine"
depends on SMP
2010-01-07 07:57:19 +03:00
select PADATA
select CRYPTO_MANAGER
select CRYPTO_AEAD
help
This converts an arbitrary crypto algorithm into a parallel
algorithm that executes in kernel threads.
2008-04-05 17:04:48 +04:00
config CRYPTO_CRYPTD
tristate "Software async crypto daemon"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2008-05-14 17:23:00 +04:00
select CRYPTO_HASH
2008-04-05 17:04:48 +04:00
select CRYPTO_MANAGER
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
This is a generic software asynchronous crypto daemon that
converts an arbitrary synchronous software crypto algorithm
into an asynchronous algorithm that executes in a kernel thread.
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_AUTHENC
tristate "Authenc support"
select CRYPTO_AEAD
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2008-04-05 17:04:48 +04:00
select CRYPTO_MANAGER
select CRYPTO_HASH
2015-08-04 16:23:14 +03:00
select CRYPTO_NULL
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
Authenc: Combined mode wrapper for IPsec.
This is required for IPSec.
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_TEST
tristate "Testing module"
2020-11-20 14:04:32 +03:00
depends on m || EXPERT
2008-07-31 13:08:25 +04:00
select CRYPTO_MANAGER
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
Quick & dirty crypto test module.
2005-04-17 02:20:36 +04:00
2016-11-22 15:08:25 +03:00
config CRYPTO_SIMD
tristate
2012-06-18 15:06:58 +04:00
select CRYPTO_CRYPTD
2016-01-26 15:25:39 +03:00
config CRYPTO_ENGINE
tristate
2019-04-11 18:51:18 +03:00
comment "Public-key cryptography"
config CRYPTO_RSA
tristate "RSA algorithm"
select CRYPTO_AKCIPHER
select CRYPTO_MANAGER
select MPILIB
select ASN1
help
Generic implementation of the RSA public key algorithm.
config CRYPTO_DH
tristate "Diffie-Hellman algorithm"
select CRYPTO_KPP
select MPILIB
help
Generic implementation of the Diffie-Hellman algorithm.
crypto: dh - implement ffdheXYZ(dh) templates
Current work on NVME in-band authentication support ([1]) needs to invoke
DH with the FFDHE safe-prime group parameters specified in RFC 7919.
Introduce a new CRYPTO_DH_RFC7919_GROUPS Kconfig option. If enabled, make
dh_generic register a couple of ffdheXYZ(dh) templates, one for each group:
ffdhe2048(dh), ffdhe3072(dh), ffdhe4096(dh), ffdhe6144(dh) and
ffdhe8192(dh). Their respective ->set_secret() expects a (serialized)
struct dh, just like the underlying "dh" implementation does, but with the
P and G values unset so that the safe-prime constants for the given group
can be filled in by the wrapping template.
Internally, a struct dh_safe_prime instance is being defined for each of
the ffdheXYZ(dh) templates as appropriate. In order to prepare for future
key generation, fill in the maximum security strength values as specified
by SP800-56Arev3 on the go, even though they're not needed at this point
yet.
Implement the respective ffdheXYZ(dh) crypto_template's ->create() by
simply forwarding any calls to the __dh_safe_prime_create() helper
introduced with the previous commit, passing the associated dh_safe_prime
in addition to the received ->create() arguments.
[1] https://lore.kernel.org/r/20211202152358.60116-1-hare@suse.de
Signed-off-by: Nicolai Stange <nstange@suse.de>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-02-21 15:10:53 +03:00
config CRYPTO_DH_RFC7919_GROUPS
bool "Support for RFC 7919 FFDHE group parameters"
depends on CRYPTO_DH
2022-02-21 15:10:55 +03:00
select CRYPTO_RNG_DEFAULT
crypto: dh - implement ffdheXYZ(dh) templates
Current work on NVME in-band authentication support ([1]) needs to invoke
DH with the FFDHE safe-prime group parameters specified in RFC 7919.
Introduce a new CRYPTO_DH_RFC7919_GROUPS Kconfig option. If enabled, make
dh_generic register a couple of ffdheXYZ(dh) templates, one for each group:
ffdhe2048(dh), ffdhe3072(dh), ffdhe4096(dh), ffdhe6144(dh) and
ffdhe8192(dh). Their respective ->set_secret() expects a (serialized)
struct dh, just like the underlying "dh" implementation does, but with the
P and G values unset so that the safe-prime constants for the given group
can be filled in by the wrapping template.
Internally, a struct dh_safe_prime instance is being defined for each of
the ffdheXYZ(dh) templates as appropriate. In order to prepare for future
key generation, fill in the maximum security strength values as specified
by SP800-56Arev3 on the go, even though they're not needed at this point
yet.
Implement the respective ffdheXYZ(dh) crypto_template's ->create() by
simply forwarding any calls to the __dh_safe_prime_create() helper
introduced with the previous commit, passing the associated dh_safe_prime
in addition to the received ->create() arguments.
[1] https://lore.kernel.org/r/20211202152358.60116-1-hare@suse.de
Signed-off-by: Nicolai Stange <nstange@suse.de>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-02-21 15:10:53 +03:00
help
Provide support for RFC 7919 FFDHE group parameters. If unsure, say N.
2019-04-11 18:51:19 +03:00
config CRYPTO_ECC
tristate
2021-09-20 13:05:35 +03:00
select CRYPTO_RNG_DEFAULT
2019-04-11 18:51:19 +03:00
2019-04-11 18:51:18 +03:00
config CRYPTO_ECDH
tristate "ECDH algorithm"
2019-04-11 18:51:19 +03:00
select CRYPTO_ECC
2019-04-11 18:51:18 +03:00
select CRYPTO_KPP
help
Generic implementation of the ECDH algorithm
2021-03-17 00:07:32 +03:00
config CRYPTO_ECDSA
tristate "ECDSA (NIST P192, P256 etc.) algorithm"
select CRYPTO_ECC
select CRYPTO_AKCIPHER
select ASN1
help
Elliptic Curve Digital Signature Algorithm (NIST P192, P256 etc.)
is A NIST cryptographic standard algorithm. Only signature verification
is implemented.
crypto: ecrdsa - add EC-RDSA (GOST 34.10) algorithm
Add Elliptic Curve Russian Digital Signature Algorithm (GOST R
34.10-2012, RFC 7091, ISO/IEC 14888-3) is one of the Russian (and since
2018 the CIS countries) cryptographic standard algorithms (called GOST
algorithms). Only signature verification is supported, with intent to be
used in the IMA.
Summary of the changes:
* crypto/Kconfig:
- EC-RDSA is added into Public-key cryptography section.
* crypto/Makefile:
- ecrdsa objects are added.
* crypto/asymmetric_keys/x509_cert_parser.c:
- Recognize EC-RDSA and Streebog OIDs.
* include/linux/oid_registry.h:
- EC-RDSA OIDs are added to the enum. Also, a two currently not
implemented curve OIDs are added for possible extension later (to
not change numbering and grouping).
* crypto/ecc.c:
- Kenneth MacKay copyright date is updated to 2014, because
vli_mmod_slow, ecc_point_add, ecc_point_mult_shamir are based on his
code from micro-ecc.
- Functions needed for ecrdsa are EXPORT_SYMBOL'ed.
- New functions:
vli_is_negative - helper to determine sign of vli;
vli_from_be64 - unpack big-endian array into vli (used for
a signature);
vli_from_le64 - unpack little-endian array into vli (used for
a public key);
vli_uadd, vli_usub - add/sub u64 value to/from vli (used for
increment/decrement);
mul_64_64 - optimized to use __int128 where appropriate, this speeds
up point multiplication (and as a consequence signature
verification) by the factor of 1.5-2;
vli_umult - multiply vli by a small value (speeds up point
multiplication by another factor of 1.5-2, depending on vli sizes);
vli_mmod_special - module reduction for some form of Pseudo-Mersenne
primes (used for the curves A);
vli_mmod_special2 - module reduction for another form of
Pseudo-Mersenne primes (used for the curves B);
vli_mmod_barrett - module reduction using pre-computed value (used
for the curve C);
vli_mmod_slow - more general module reduction which is much slower
(used when the modulus is subgroup order);
vli_mod_mult_slow - modular multiplication;
ecc_point_add - add two points;
ecc_point_mult_shamir - add two points multiplied by scalars in one
combined multiplication (this gives speed up by another factor 2 in
compare to two separate multiplications).
ecc_is_pubkey_valid_partial - additional samity check is added.
- Updated vli_mmod_fast with non-strict heuristic to call optimal
module reduction function depending on the prime value;
- All computations for the previously defined (two NIST) curves should
not unaffected.
* crypto/ecc.h:
- Newly exported functions are documented.
* crypto/ecrdsa_defs.h
- Five curves are defined.
* crypto/ecrdsa.c:
- Signature verification is implemented.
* crypto/ecrdsa_params.asn1, crypto/ecrdsa_pub_key.asn1:
- Templates for BER decoder for EC-RDSA parameters and public key.
Cc: linux-integrity@vger.kernel.org
Signed-off-by: Vitaly Chikunov <vt@altlinux.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-04-11 18:51:20 +03:00
config CRYPTO_ECRDSA
tristate "EC-RDSA (GOST 34.10) algorithm"
select CRYPTO_ECC
select CRYPTO_AKCIPHER
select CRYPTO_STREEBOG
2019-04-24 04:32:40 +03:00
select OID_REGISTRY
select ASN1
crypto: ecrdsa - add EC-RDSA (GOST 34.10) algorithm
Add Elliptic Curve Russian Digital Signature Algorithm (GOST R
34.10-2012, RFC 7091, ISO/IEC 14888-3) is one of the Russian (and since
2018 the CIS countries) cryptographic standard algorithms (called GOST
algorithms). Only signature verification is supported, with intent to be
used in the IMA.
Summary of the changes:
* crypto/Kconfig:
- EC-RDSA is added into Public-key cryptography section.
* crypto/Makefile:
- ecrdsa objects are added.
* crypto/asymmetric_keys/x509_cert_parser.c:
- Recognize EC-RDSA and Streebog OIDs.
* include/linux/oid_registry.h:
- EC-RDSA OIDs are added to the enum. Also, a two currently not
implemented curve OIDs are added for possible extension later (to
not change numbering and grouping).
* crypto/ecc.c:
- Kenneth MacKay copyright date is updated to 2014, because
vli_mmod_slow, ecc_point_add, ecc_point_mult_shamir are based on his
code from micro-ecc.
- Functions needed for ecrdsa are EXPORT_SYMBOL'ed.
- New functions:
vli_is_negative - helper to determine sign of vli;
vli_from_be64 - unpack big-endian array into vli (used for
a signature);
vli_from_le64 - unpack little-endian array into vli (used for
a public key);
vli_uadd, vli_usub - add/sub u64 value to/from vli (used for
increment/decrement);
mul_64_64 - optimized to use __int128 where appropriate, this speeds
up point multiplication (and as a consequence signature
verification) by the factor of 1.5-2;
vli_umult - multiply vli by a small value (speeds up point
multiplication by another factor of 1.5-2, depending on vli sizes);
vli_mmod_special - module reduction for some form of Pseudo-Mersenne
primes (used for the curves A);
vli_mmod_special2 - module reduction for another form of
Pseudo-Mersenne primes (used for the curves B);
vli_mmod_barrett - module reduction using pre-computed value (used
for the curve C);
vli_mmod_slow - more general module reduction which is much slower
(used when the modulus is subgroup order);
vli_mod_mult_slow - modular multiplication;
ecc_point_add - add two points;
ecc_point_mult_shamir - add two points multiplied by scalars in one
combined multiplication (this gives speed up by another factor 2 in
compare to two separate multiplications).
ecc_is_pubkey_valid_partial - additional samity check is added.
- Updated vli_mmod_fast with non-strict heuristic to call optimal
module reduction function depending on the prime value;
- All computations for the previously defined (two NIST) curves should
not unaffected.
* crypto/ecc.h:
- Newly exported functions are documented.
* crypto/ecrdsa_defs.h
- Five curves are defined.
* crypto/ecrdsa.c:
- Signature verification is implemented.
* crypto/ecrdsa_params.asn1, crypto/ecrdsa_pub_key.asn1:
- Templates for BER decoder for EC-RDSA parameters and public key.
Cc: linux-integrity@vger.kernel.org
Signed-off-by: Vitaly Chikunov <vt@altlinux.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-04-11 18:51:20 +03:00
help
Elliptic Curve Russian Digital Signature Algorithm (GOST R 34.10-2012,
RFC 7091, ISO/IEC 14888-3:2018) is one of the Russian cryptographic
standard algorithms (called GOST algorithms). Only signature verification
is implemented.
2020-09-20 19:20:57 +03:00
config CRYPTO_SM2
tristate "SM2 algorithm"
2022-03-14 06:11:01 +03:00
select CRYPTO_SM3
2020-09-20 19:20:57 +03:00
select CRYPTO_AKCIPHER
select CRYPTO_MANAGER
select MPILIB
select ASN1
help
Generic implementation of the SM2 public key algorithm. It was
published by State Encryption Management Bureau, China.
as specified by OSCCA GM/T 0003.1-2012 -- 0003.5-2012.
References:
https://tools.ietf.org/html/draft-shen-sm2-ecdsa-02
http://www.oscca.gov.cn/sca/xxgk/2010-12/17/content_1002386.shtml
http://www.gmbz.org.cn/main/bzlb.html
2019-11-08 15:22:34 +03:00
config CRYPTO_CURVE25519
tristate "Curve25519 algorithm"
select CRYPTO_KPP
select CRYPTO_LIB_CURVE25519_GENERIC
2008-04-05 17:04:48 +04:00
comment "Authenticated Encryption with Associated Data"
2007-11-10 15:08:25 +03:00
2008-04-05 17:04:48 +04:00
config CRYPTO_CCM
tristate "CCM support"
select CRYPTO_CTR
2017-02-03 17:49:36 +03:00
select CRYPTO_HASH
2008-04-05 17:04:48 +04:00
select CRYPTO_AEAD
2019-05-20 19:49:46 +03:00
select CRYPTO_MANAGER
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
Support for Counter with CBC MAC. Required for IPsec.
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_GCM
tristate "GCM/GMAC support"
select CRYPTO_CTR
select CRYPTO_AEAD
2009-08-06 09:34:26 +04:00
select CRYPTO_GHASH
2013-04-07 17:43:41 +04:00
select CRYPTO_NULL
2019-05-20 19:49:46 +03:00
select CRYPTO_MANAGER
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
Support for Galois/Counter Mode (GCM) and Galois Message
Authentication Code (GMAC). Required for IPSec.
2005-04-17 02:20:36 +04:00
2015-06-01 14:44:00 +03:00
config CRYPTO_CHACHA20POLY1305
tristate "ChaCha20-Poly1305 AEAD support"
select CRYPTO_CHACHA20
select CRYPTO_POLY1305
select CRYPTO_AEAD
2019-05-20 19:49:46 +03:00
select CRYPTO_MANAGER
2015-06-01 14:44:00 +03:00
help
ChaCha20-Poly1305 AEAD support, RFC7539.
Support for the AEAD wrapper using the ChaCha20 stream cipher combined
with the Poly1305 authenticator. It is defined in RFC7539 for use in
IETF protocols.
2018-05-11 15:12:49 +03:00
config CRYPTO_AEGIS128
tristate "AEGIS-128 AEAD algorithm"
select CRYPTO_AEAD
select CRYPTO_AES # for AES S-box tables
help
Support for the AEGIS-128 dedicated AEAD algorithm.
2019-08-12 01:59:11 +03:00
config CRYPTO_AEGIS128_SIMD
bool "Support SIMD acceleration for AEGIS-128"
depends on CRYPTO_AEGIS128 && ((ARM || ARM64) && KERNEL_MODE_NEON)
default y
2008-04-05 17:04:48 +04:00
config CRYPTO_SEQIV
tristate "Sequence Number IV Generator"
select CRYPTO_AEAD
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2015-05-21 10:11:13 +03:00
select CRYPTO_NULL
2015-06-03 09:49:31 +03:00
select CRYPTO_RNG_DEFAULT
2019-05-20 19:49:46 +03:00
select CRYPTO_MANAGER
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
This IV generator generates an IV based on a sequence number by
xoring it with a salt. This algorithm is mainly useful for CTR
2005-04-17 02:20:36 +04:00
2015-05-21 10:11:15 +03:00
config CRYPTO_ECHAINIV
tristate "Encrypted Chain IV Generator"
select CRYPTO_AEAD
select CRYPTO_NULL
2015-06-03 09:49:31 +03:00
select CRYPTO_RNG_DEFAULT
2019-05-20 19:49:46 +03:00
select CRYPTO_MANAGER
2015-05-21 10:11:15 +03:00
help
This IV generator generates an IV based on the encryption of
a sequence number xored with a salt. This is the default
algorithm for CBC.
2008-04-05 17:04:48 +04:00
comment "Block modes"
2006-11-29 10:59:44 +03:00
2008-04-05 17:04:48 +04:00
config CRYPTO_CBC
tristate "CBC support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2006-10-16 15:28:58 +04:00
select CRYPTO_MANAGER
2006-09-21 05:44:08 +04:00
help
2008-04-05 17:04:48 +04:00
CBC: Cipher Block Chaining mode
This block cipher algorithm is required for IPSec.
2006-09-21 05:44:08 +04:00
2018-03-02 01:36:17 +03:00
config CRYPTO_CFB
tristate "CFB support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2018-03-02 01:36:17 +03:00
select CRYPTO_MANAGER
help
CFB: Cipher FeedBack mode
This block cipher algorithm is required for TPM2 Cryptography.
2008-04-05 17:04:48 +04:00
config CRYPTO_CTR
tristate "CTR support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2006-10-16 15:28:58 +04:00
select CRYPTO_MANAGER
2006-09-21 05:44:08 +04:00
help
2008-04-05 17:04:48 +04:00
CTR: Counter mode
2006-09-21 05:44:08 +04:00
This block cipher algorithm is required for IPSec.
2008-04-05 17:04:48 +04:00
config CRYPTO_CTS
tristate "CTS support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2019-05-20 19:49:46 +03:00
select CRYPTO_MANAGER
2008-04-05 17:04:48 +04:00
help
CTS: Cipher Text Stealing
This is the Cipher Text Stealing mode as described by
2018-11-05 15:05:01 +03:00
Section 8 of rfc2040 and referenced by rfc3962
(rfc3962 includes errata information in its Appendix A) or
CBC-CS3 as defined by NIST in Sp800-38A addendum from Oct 2010.
2008-04-05 17:04:48 +04:00
This mode is required for Kerberos gss mechanism support
for AES encryption.
2018-11-05 15:05:01 +03:00
See: https://csrc.nist.gov/publications/detail/sp/800-38a/addendum/final
2008-04-05 17:04:48 +04:00
config CRYPTO_ECB
tristate "ECB support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2006-12-16 04:09:02 +03:00
select CRYPTO_MANAGER
help
2008-04-05 17:04:48 +04:00
ECB: Electronic CodeBook mode
This is the simplest block cipher algorithm. It simply encrypts
the input block by block.
2006-12-16 04:09:02 +03:00
2006-11-26 01:43:10 +03:00
config CRYPTO_LRW
2011-12-13 14:52:51 +04:00
tristate "LRW support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2006-11-26 01:43:10 +03:00
select CRYPTO_MANAGER
select CRYPTO_GF128MUL
2022-02-10 05:31:13 +03:00
select CRYPTO_ECB
2006-11-26 01:43:10 +03:00
help
LRW: Liskov Rivest Wagner, a tweakable, non malleable, non movable
narrow block cipher mode for dm-crypt. Use it with cipher
specification string aes-lrw-benbi, the key must be 256, 320 or 384.
The first 128, 192 or 256 bits in the key are used for AES and the
rest is used to tie each cipher block to its logical position.
2018-09-20 16:18:39 +03:00
config CRYPTO_OFB
tristate "OFB support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2018-09-20 16:18:39 +03:00
select CRYPTO_MANAGER
help
OFB: the Output Feedback mode makes a block cipher into a synchronous
stream cipher. It generates keystream blocks, which are then XORed
with the plaintext blocks to get the ciphertext. Flipping a bit in the
ciphertext produces a flipped bit in the plaintext at the same
location. This property allows many error correcting codes to function
normally even when applied before encryption.
2008-04-05 17:04:48 +04:00
config CRYPTO_PCBC
tristate "PCBC support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2008-04-05 17:04:48 +04:00
select CRYPTO_MANAGER
help
PCBC: Propagating Cipher Block Chaining mode
This block cipher algorithm is required for RxRPC.
2022-05-20 21:14:53 +03:00
config CRYPTO_XCTR
tristate
select CRYPTO_SKCIPHER
select CRYPTO_MANAGER
help
XCTR: XOR Counter mode. This blockcipher mode is a variant of CTR mode
using XORs and little-endian addition rather than big-endian arithmetic.
XCTR mode is used to implement HCTR2.
2007-09-19 16:23:13 +04:00
config CRYPTO_XTS
2011-12-13 14:52:56 +04:00
tristate "XTS support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2007-09-19 16:23:13 +04:00
select CRYPTO_MANAGER
2017-02-23 10:38:26 +03:00
select CRYPTO_ECB
2007-09-19 16:23:13 +04:00
help
XTS: IEEE1619/D16 narrow block cipher use with aes-xts-plain,
key size 256, 384 or 512 bits. This implementation currently
can't handle a sectorsize which is not a multiple of 16 bytes.
2015-09-21 21:58:56 +03:00
config CRYPTO_KEYWRAP
tristate "Key wrapping support"
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2019-05-20 19:49:46 +03:00
select CRYPTO_MANAGER
2015-09-21 21:58:56 +03:00
help
Support for key wrapping (NIST SP800-38F / RFC3394) without
padding.
2018-11-17 04:26:29 +03:00
config CRYPTO_NHPOLY1305
tristate
select CRYPTO_HASH
2019-11-08 15:22:19 +03:00
select CRYPTO_LIB_POLY1305_GENERIC
2018-11-17 04:26:29 +03:00
crypto: adiantum - add Adiantum support
Add support for the Adiantum encryption mode. Adiantum was designed by
Paul Crowley and is specified by our paper:
Adiantum: length-preserving encryption for entry-level processors
(https://eprint.iacr.org/2018/720.pdf)
See our paper for full details; this patch only provides an overview.
Adiantum is a tweakable, length-preserving encryption mode designed for
fast and secure disk encryption, especially on CPUs without dedicated
crypto instructions. Adiantum encrypts each sector using the XChaCha12
stream cipher, two passes of an ε-almost-∆-universal (εA∆U) hash
function, and an invocation of the AES-256 block cipher on a single
16-byte block. On CPUs without AES instructions, Adiantum is much
faster than AES-XTS; for example, on ARM Cortex-A7, on 4096-byte sectors
Adiantum encryption is about 4 times faster than AES-256-XTS encryption,
and decryption about 5 times faster.
Adiantum is a specialization of the more general HBSH construction. Our
earlier proposal, HPolyC, was also a HBSH specialization, but it used a
different εA∆U hash function, one based on Poly1305 only. Adiantum's
εA∆U hash function, which is based primarily on the "NH" hash function
like that used in UMAC (RFC4418), is about twice as fast as HPolyC's;
consequently, Adiantum is about 20% faster than HPolyC.
This speed comes with no loss of security: Adiantum is provably just as
secure as HPolyC, in fact slightly *more* secure. Like HPolyC,
Adiantum's security is reducible to that of XChaCha12 and AES-256,
subject to a security bound. XChaCha12 itself has a security reduction
to ChaCha12. Therefore, one need not "trust" Adiantum; one need only
trust ChaCha12 and AES-256. Note that the εA∆U hash function is only
used for its proven combinatorical properties so cannot be "broken".
Adiantum is also a true wide-block encryption mode, so flipping any
plaintext bit in the sector scrambles the entire ciphertext, and vice
versa. No other such mode is available in the kernel currently; doing
the same with XTS scrambles only 16 bytes. Adiantum also supports
arbitrary-length tweaks and naturally supports any length input >= 16
bytes without needing "ciphertext stealing".
For the stream cipher, Adiantum uses XChaCha12 rather than XChaCha20 in
order to make encryption feasible on the widest range of devices.
Although the 20-round variant is quite popular, the best known attacks
on ChaCha are on only 7 rounds, so ChaCha12 still has a substantial
security margin; in fact, larger than AES-256's. 12-round Salsa20 is
also the eSTREAM recommendation. For the block cipher, Adiantum uses
AES-256, despite it having a lower security margin than XChaCha12 and
needing table lookups, due to AES's extensive adoption and analysis
making it the obvious first choice. Nevertheless, for flexibility this
patch also permits the "adiantum" template to be instantiated with
XChaCha20 and/or with an alternate block cipher.
We need Adiantum support in the kernel for use in dm-crypt and fscrypt,
where currently the only other suitable options are block cipher modes
such as AES-XTS. A big problem with this is that many low-end mobile
devices (e.g. Android Go phones sold primarily in developing countries,
as well as some smartwatches) still have CPUs that lack AES
instructions, e.g. ARM Cortex-A7. Sadly, AES-XTS encryption is much too
slow to be viable on these devices. We did find that some "lightweight"
block ciphers are fast enough, but these suffer from problems such as
not having much cryptanalysis or being too controversial.
The ChaCha stream cipher has excellent performance but is insecure to
use directly for disk encryption, since each sector's IV is reused each
time it is overwritten. Even restricting the threat model to offline
attacks only isn't enough, since modern flash storage devices don't
guarantee that "overwrites" are really overwrites, due to wear-leveling.
Adiantum avoids this problem by constructing a
"tweakable super-pseudorandom permutation"; this is the strongest
possible security model for length-preserving encryption.
Of course, storing random nonces along with the ciphertext would be the
ideal solution. But doing that with existing hardware and filesystems
runs into major practical problems; in most cases it would require data
journaling (like dm-integrity) which severely degrades performance.
Thus, for now length-preserving encryption is still needed.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-17 04:26:31 +03:00
config CRYPTO_ADIANTUM
tristate "Adiantum support"
select CRYPTO_CHACHA20
2019-11-08 15:22:19 +03:00
select CRYPTO_LIB_POLY1305_GENERIC
crypto: adiantum - add Adiantum support
Add support for the Adiantum encryption mode. Adiantum was designed by
Paul Crowley and is specified by our paper:
Adiantum: length-preserving encryption for entry-level processors
(https://eprint.iacr.org/2018/720.pdf)
See our paper for full details; this patch only provides an overview.
Adiantum is a tweakable, length-preserving encryption mode designed for
fast and secure disk encryption, especially on CPUs without dedicated
crypto instructions. Adiantum encrypts each sector using the XChaCha12
stream cipher, two passes of an ε-almost-∆-universal (εA∆U) hash
function, and an invocation of the AES-256 block cipher on a single
16-byte block. On CPUs without AES instructions, Adiantum is much
faster than AES-XTS; for example, on ARM Cortex-A7, on 4096-byte sectors
Adiantum encryption is about 4 times faster than AES-256-XTS encryption,
and decryption about 5 times faster.
Adiantum is a specialization of the more general HBSH construction. Our
earlier proposal, HPolyC, was also a HBSH specialization, but it used a
different εA∆U hash function, one based on Poly1305 only. Adiantum's
εA∆U hash function, which is based primarily on the "NH" hash function
like that used in UMAC (RFC4418), is about twice as fast as HPolyC's;
consequently, Adiantum is about 20% faster than HPolyC.
This speed comes with no loss of security: Adiantum is provably just as
secure as HPolyC, in fact slightly *more* secure. Like HPolyC,
Adiantum's security is reducible to that of XChaCha12 and AES-256,
subject to a security bound. XChaCha12 itself has a security reduction
to ChaCha12. Therefore, one need not "trust" Adiantum; one need only
trust ChaCha12 and AES-256. Note that the εA∆U hash function is only
used for its proven combinatorical properties so cannot be "broken".
Adiantum is also a true wide-block encryption mode, so flipping any
plaintext bit in the sector scrambles the entire ciphertext, and vice
versa. No other such mode is available in the kernel currently; doing
the same with XTS scrambles only 16 bytes. Adiantum also supports
arbitrary-length tweaks and naturally supports any length input >= 16
bytes without needing "ciphertext stealing".
For the stream cipher, Adiantum uses XChaCha12 rather than XChaCha20 in
order to make encryption feasible on the widest range of devices.
Although the 20-round variant is quite popular, the best known attacks
on ChaCha are on only 7 rounds, so ChaCha12 still has a substantial
security margin; in fact, larger than AES-256's. 12-round Salsa20 is
also the eSTREAM recommendation. For the block cipher, Adiantum uses
AES-256, despite it having a lower security margin than XChaCha12 and
needing table lookups, due to AES's extensive adoption and analysis
making it the obvious first choice. Nevertheless, for flexibility this
patch also permits the "adiantum" template to be instantiated with
XChaCha20 and/or with an alternate block cipher.
We need Adiantum support in the kernel for use in dm-crypt and fscrypt,
where currently the only other suitable options are block cipher modes
such as AES-XTS. A big problem with this is that many low-end mobile
devices (e.g. Android Go phones sold primarily in developing countries,
as well as some smartwatches) still have CPUs that lack AES
instructions, e.g. ARM Cortex-A7. Sadly, AES-XTS encryption is much too
slow to be viable on these devices. We did find that some "lightweight"
block ciphers are fast enough, but these suffer from problems such as
not having much cryptanalysis or being too controversial.
The ChaCha stream cipher has excellent performance but is insecure to
use directly for disk encryption, since each sector's IV is reused each
time it is overwritten. Even restricting the threat model to offline
attacks only isn't enough, since modern flash storage devices don't
guarantee that "overwrites" are really overwrites, due to wear-leveling.
Adiantum avoids this problem by constructing a
"tweakable super-pseudorandom permutation"; this is the strongest
possible security model for length-preserving encryption.
Of course, storing random nonces along with the ciphertext would be the
ideal solution. But doing that with existing hardware and filesystems
runs into major practical problems; in most cases it would require data
journaling (like dm-integrity) which severely degrades performance.
Thus, for now length-preserving encryption is still needed.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-17 04:26:31 +03:00
select CRYPTO_NHPOLY1305
2019-05-20 19:49:46 +03:00
select CRYPTO_MANAGER
crypto: adiantum - add Adiantum support
Add support for the Adiantum encryption mode. Adiantum was designed by
Paul Crowley and is specified by our paper:
Adiantum: length-preserving encryption for entry-level processors
(https://eprint.iacr.org/2018/720.pdf)
See our paper for full details; this patch only provides an overview.
Adiantum is a tweakable, length-preserving encryption mode designed for
fast and secure disk encryption, especially on CPUs without dedicated
crypto instructions. Adiantum encrypts each sector using the XChaCha12
stream cipher, two passes of an ε-almost-∆-universal (εA∆U) hash
function, and an invocation of the AES-256 block cipher on a single
16-byte block. On CPUs without AES instructions, Adiantum is much
faster than AES-XTS; for example, on ARM Cortex-A7, on 4096-byte sectors
Adiantum encryption is about 4 times faster than AES-256-XTS encryption,
and decryption about 5 times faster.
Adiantum is a specialization of the more general HBSH construction. Our
earlier proposal, HPolyC, was also a HBSH specialization, but it used a
different εA∆U hash function, one based on Poly1305 only. Adiantum's
εA∆U hash function, which is based primarily on the "NH" hash function
like that used in UMAC (RFC4418), is about twice as fast as HPolyC's;
consequently, Adiantum is about 20% faster than HPolyC.
This speed comes with no loss of security: Adiantum is provably just as
secure as HPolyC, in fact slightly *more* secure. Like HPolyC,
Adiantum's security is reducible to that of XChaCha12 and AES-256,
subject to a security bound. XChaCha12 itself has a security reduction
to ChaCha12. Therefore, one need not "trust" Adiantum; one need only
trust ChaCha12 and AES-256. Note that the εA∆U hash function is only
used for its proven combinatorical properties so cannot be "broken".
Adiantum is also a true wide-block encryption mode, so flipping any
plaintext bit in the sector scrambles the entire ciphertext, and vice
versa. No other such mode is available in the kernel currently; doing
the same with XTS scrambles only 16 bytes. Adiantum also supports
arbitrary-length tweaks and naturally supports any length input >= 16
bytes without needing "ciphertext stealing".
For the stream cipher, Adiantum uses XChaCha12 rather than XChaCha20 in
order to make encryption feasible on the widest range of devices.
Although the 20-round variant is quite popular, the best known attacks
on ChaCha are on only 7 rounds, so ChaCha12 still has a substantial
security margin; in fact, larger than AES-256's. 12-round Salsa20 is
also the eSTREAM recommendation. For the block cipher, Adiantum uses
AES-256, despite it having a lower security margin than XChaCha12 and
needing table lookups, due to AES's extensive adoption and analysis
making it the obvious first choice. Nevertheless, for flexibility this
patch also permits the "adiantum" template to be instantiated with
XChaCha20 and/or with an alternate block cipher.
We need Adiantum support in the kernel for use in dm-crypt and fscrypt,
where currently the only other suitable options are block cipher modes
such as AES-XTS. A big problem with this is that many low-end mobile
devices (e.g. Android Go phones sold primarily in developing countries,
as well as some smartwatches) still have CPUs that lack AES
instructions, e.g. ARM Cortex-A7. Sadly, AES-XTS encryption is much too
slow to be viable on these devices. We did find that some "lightweight"
block ciphers are fast enough, but these suffer from problems such as
not having much cryptanalysis or being too controversial.
The ChaCha stream cipher has excellent performance but is insecure to
use directly for disk encryption, since each sector's IV is reused each
time it is overwritten. Even restricting the threat model to offline
attacks only isn't enough, since modern flash storage devices don't
guarantee that "overwrites" are really overwrites, due to wear-leveling.
Adiantum avoids this problem by constructing a
"tweakable super-pseudorandom permutation"; this is the strongest
possible security model for length-preserving encryption.
Of course, storing random nonces along with the ciphertext would be the
ideal solution. But doing that with existing hardware and filesystems
runs into major practical problems; in most cases it would require data
journaling (like dm-integrity) which severely degrades performance.
Thus, for now length-preserving encryption is still needed.
Signed-off-by: Eric Biggers <ebiggers@google.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-17 04:26:31 +03:00
help
Adiantum is a tweakable, length-preserving encryption mode
designed for fast and secure disk encryption, especially on
CPUs without dedicated crypto instructions. It encrypts
each sector using the XChaCha12 stream cipher, two passes of
an ε-almost-∆-universal hash function, and an invocation of
the AES-256 block cipher on a single 16-byte block. On CPUs
without AES instructions, Adiantum is much faster than
AES-XTS.
Adiantum's security is provably reducible to that of its
underlying stream and block ciphers, subject to a security
bound. Unlike XTS, Adiantum is a true wide-block encryption
mode, so it actually provides an even stronger notion of
security than XTS, subject to the security bound.
If unsure, say N.
crypto: hctr2 - Add HCTR2 support
Add support for HCTR2 as a template. HCTR2 is a length-preserving
encryption mode that is efficient on processors with instructions to
accelerate AES and carryless multiplication, e.g. x86 processors with
AES-NI and CLMUL, and ARM processors with the ARMv8 Crypto Extensions.
As a length-preserving encryption mode, HCTR2 is suitable for
applications such as storage encryption where ciphertext expansion is
not possible, and thus authenticated encryption cannot be used.
Currently, such applications usually use XTS, or in some cases Adiantum.
XTS has the disadvantage that it is a narrow-block mode: a bitflip will
only change 16 bytes in the resulting ciphertext or plaintext. This
reveals more information to an attacker than necessary.
HCTR2 is a wide-block mode, so it provides a stronger security property:
a bitflip will change the entire message. HCTR2 is somewhat similar to
Adiantum, which is also a wide-block mode. However, HCTR2 is designed
to take advantage of existing crypto instructions, while Adiantum
targets devices without such hardware support. Adiantum is also
designed with longer messages in mind, while HCTR2 is designed to be
efficient even on short messages.
HCTR2 requires POLYVAL and XCTR as components. More information on
HCTR2 can be found here: "Length-preserving encryption with HCTR2":
https://eprint.iacr.org/2021/1441.pdf
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-05-20 21:14:55 +03:00
config CRYPTO_HCTR2
tristate "HCTR2 support"
select CRYPTO_XCTR
select CRYPTO_POLYVAL
select CRYPTO_MANAGER
help
HCTR2 is a length-preserving encryption mode for storage encryption that
is efficient on processors with instructions to accelerate AES and
carryless multiplication, e.g. x86 processors with AES-NI and CLMUL, and
ARM processors with the ARMv8 crypto extensions.
2019-08-19 17:17:33 +03:00
config CRYPTO_ESSIV
tristate "ESSIV support for block encryption"
select CRYPTO_AUTHENC
help
Encrypted salt-sector initialization vector (ESSIV) is an IV
generation method that is used in some cases by fscrypt and/or
dm-crypt. It uses the hash of the block encryption key as the
symmetric key for a block encryption pass applied to the input
IV, making low entropy IV sources more suitable for block
encryption.
This driver implements a crypto API template that can be
2020-01-12 19:58:58 +03:00
instantiated either as an skcipher or as an AEAD (depending on the
2019-08-19 17:17:33 +03:00
type of the first template argument), and which defers encryption
and decryption requests to the encapsulated cipher after applying
2020-01-12 19:58:58 +03:00
ESSIV to the input IV. Note that in the AEAD case, it is assumed
2019-08-19 17:17:33 +03:00
that the keys are presented in the same format used by the authenc
template, and that the IV appears at the end of the authenticated
associated data (AAD) region (which is how dm-crypt uses it.)
Note that the use of ESSIV is not recommended for new deployments,
and so this only needs to be enabled when interoperability with
existing encrypted volumes of filesystems is required, or when
building for a particular system that requires it (e.g., when
the SoC in question has accelerated CBC but not XTS, making CBC
combined with ESSIV the only feasible mode for h/w accelerated
block encryption)
2008-04-05 17:04:48 +04:00
comment "Hash modes"
2013-04-08 11:48:44 +04:00
config CRYPTO_CMAC
tristate "CMAC support"
select CRYPTO_HASH
select CRYPTO_MANAGER
help
Cipher-based Message Authentication Code (CMAC) specified by
The National Institute of Standards and Technology (NIST).
https://tools.ietf.org/html/rfc4493
http://csrc.nist.gov/publications/nistpubs/800-38B/SP_800-38B.pdf
2008-04-05 17:04:48 +04:00
config CRYPTO_HMAC
tristate "HMAC support"
select CRYPTO_HASH
[CRYPTO] ctr: Add CTR (Counter) block cipher mode
This patch implements CTR mode for IPsec.
It is based off of RFC 3686.
Please note:
1. CTR turns a block cipher into a stream cipher.
Encryption is done in blocks, however the last block
may be a partial block.
A "counter block" is encrypted, creating a keystream
that is xor'ed with the plaintext. The counter portion
of the counter block is incremented after each block
of plaintext is encrypted.
Decryption is performed in same manner.
2. The CTR counterblock is composed of,
nonce + IV + counter
The size of the counterblock is equivalent to the
blocksize of the cipher.
sizeof(nonce) + sizeof(IV) + sizeof(counter) = blocksize
The CTR template requires the name of the cipher
algorithm, the sizeof the nonce, and the sizeof the iv.
ctr(cipher,sizeof_nonce,sizeof_iv)
So for example,
ctr(aes,4,8)
specifies the counterblock will be composed of 4 bytes
from a nonce, 8 bytes from the iv, and 4 bytes for counter
since aes has a blocksize of 16 bytes.
3. The counter portion of the counter block is stored
in big endian for conformance to rfc 3686.
Signed-off-by: Joy Latten <latten@austin.ibm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-10-23 04:50:32 +04:00
select CRYPTO_MANAGER
help
2008-04-05 17:04:48 +04:00
HMAC: Keyed-Hashing for Message Authentication (RFC2104).
This is required for IPSec.
[CRYPTO] ctr: Add CTR (Counter) block cipher mode
This patch implements CTR mode for IPsec.
It is based off of RFC 3686.
Please note:
1. CTR turns a block cipher into a stream cipher.
Encryption is done in blocks, however the last block
may be a partial block.
A "counter block" is encrypted, creating a keystream
that is xor'ed with the plaintext. The counter portion
of the counter block is incremented after each block
of plaintext is encrypted.
Decryption is performed in same manner.
2. The CTR counterblock is composed of,
nonce + IV + counter
The size of the counterblock is equivalent to the
blocksize of the cipher.
sizeof(nonce) + sizeof(IV) + sizeof(counter) = blocksize
The CTR template requires the name of the cipher
algorithm, the sizeof the nonce, and the sizeof the iv.
ctr(cipher,sizeof_nonce,sizeof_iv)
So for example,
ctr(aes,4,8)
specifies the counterblock will be composed of 4 bytes
from a nonce, 8 bytes from the iv, and 4 bytes for counter
since aes has a blocksize of 16 bytes.
3. The counter portion of the counter block is stored
in big endian for conformance to rfc 3686.
Signed-off-by: Joy Latten <latten@austin.ibm.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-10-23 04:50:32 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_XCBC
tristate "XCBC support"
select CRYPTO_HASH
select CRYPTO_MANAGER
2008-03-24 16:26:16 +03:00
help
2008-04-05 17:04:48 +04:00
XCBC: Keyed-Hashing with encryption algorithm
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https://www.ietf.org/rfc/rfc3566.txt
2008-04-05 17:04:48 +04:00
http://csrc.nist.gov/encryption/modes/proposedmodes/
xcbc-mac/xcbc-mac-spec.pdf
2008-03-24 16:26:16 +03:00
2009-09-02 14:05:22 +04:00
config CRYPTO_VMAC
tristate "VMAC support"
select CRYPTO_HASH
select CRYPTO_MANAGER
help
VMAC is a message authentication algorithm designed for
very high speed on 64-bit architectures.
See also:
2020-07-19 19:49:59 +03:00
<https://fastcrypto.org/vmac>
2009-09-02 14:05:22 +04:00
2008-04-05 17:04:48 +04:00
comment "Digest"
2007-11-26 17:24:11 +03:00
2008-04-05 17:04:48 +04:00
config CRYPTO_CRC32C
tristate "CRC32c CRC algorithm"
2008-07-08 16:54:28 +04:00
select CRYPTO_HASH
2012-03-24 02:02:25 +04:00
select CRC32
2007-12-12 15:25:13 +03:00
help
2008-04-05 17:04:48 +04:00
Castagnoli, et al Cyclic Redundancy-Check Algorithm. Used
by iSCSI for header and data digests and by others.
2008-11-07 10:11:47 +03:00
See Castagnoli93. Module will be crc32c.
2007-12-12 15:25:13 +03:00
2013-01-10 18:54:59 +04:00
config CRYPTO_CRC32
tristate "CRC32 CRC algorithm"
select CRYPTO_HASH
select CRC32
help
CRC-32-IEEE 802.3 cyclic redundancy-check algorithm.
Shash crypto api wrappers to crc32_le function.
2019-05-30 09:52:57 +03:00
config CRYPTO_XXHASH
tristate "xxHash hash algorithm"
select CRYPTO_HASH
select XXHASH
help
xxHash non-cryptographic hash algorithm. Extremely fast, working at
speeds close to RAM limits.
2019-10-24 19:28:31 +03:00
config CRYPTO_BLAKE2B
tristate "BLAKE2b digest algorithm"
select CRYPTO_HASH
help
Implementation of cryptographic hash function BLAKE2b (or just BLAKE2),
optimized for 64bit platforms and can produce digests of any size
between 1 to 64. The keyed hash is also implemented.
This module provides the following algorithms:
- blake2b-160
- blake2b-256
- blake2b-384
- blake2b-512
See https://blake2.net for further information.
2013-09-07 06:56:26 +04:00
config CRYPTO_CRCT10DIF
tristate "CRCT10DIF algorithm"
select CRYPTO_HASH
help
CRC T10 Data Integrity Field computation is being cast as
a crypto transform. This allows for faster crc t10 diff
transforms to be used if they are available.
2022-03-03 23:13:10 +03:00
config CRYPTO_CRC64_ROCKSOFT
tristate "Rocksoft Model CRC64 algorithm"
depends on CRC64
select CRYPTO_HASH
2009-08-06 09:32:38 +04:00
config CRYPTO_GHASH
2019-07-20 09:09:18 +03:00
tristate "GHASH hash function"
2009-08-06 09:32:38 +04:00
select CRYPTO_GF128MUL
2016-01-25 19:51:21 +03:00
select CRYPTO_HASH
2009-08-06 09:32:38 +04:00
help
2019-07-20 09:09:18 +03:00
GHASH is the hash function used in GCM (Galois/Counter Mode).
It is not a general-purpose cryptographic hash function.
2009-08-06 09:32:38 +04:00
2022-05-20 21:14:54 +03:00
config CRYPTO_POLYVAL
tristate
select CRYPTO_GF128MUL
select CRYPTO_HASH
help
POLYVAL is the hash function used in HCTR2. It is not a general-purpose
cryptographic hash function.
2015-06-01 14:43:58 +03:00
config CRYPTO_POLY1305
tristate "Poly1305 authenticator algorithm"
2016-01-25 19:51:21 +03:00
select CRYPTO_HASH
2019-11-08 15:22:19 +03:00
select CRYPTO_LIB_POLY1305_GENERIC
2015-06-01 14:43:58 +03:00
help
Poly1305 authenticator algorithm, RFC7539.
Poly1305 is an authenticator algorithm designed by Daniel J. Bernstein.
It is used for the ChaCha20-Poly1305 AEAD, specified in RFC7539 for use
in IETF protocols. This is the portable C implementation of Poly1305.
2008-04-05 17:04:48 +04:00
config CRYPTO_MD4
tristate "MD4 digest algorithm"
2008-12-03 14:55:27 +03:00
select CRYPTO_HASH
2007-04-16 14:49:20 +04:00
help
2008-04-05 17:04:48 +04:00
MD4 message digest algorithm (RFC1320).
2007-04-16 14:49:20 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_MD5
tristate "MD5 digest algorithm"
2008-12-03 14:57:12 +03:00
select CRYPTO_HASH
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
MD5 message digest algorithm (RFC1321).
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_MICHAEL_MIC
tristate "Michael MIC keyed digest algorithm"
2008-12-07 14:35:38 +03:00
select CRYPTO_HASH
2006-12-16 04:13:14 +03:00
help
2008-04-05 17:04:48 +04:00
Michael MIC is used for message integrity protection in TKIP
(IEEE 802.11i). This algorithm is required for TKIP, but it
should not be used for other purposes because of the weakness
of the algorithm.
2006-12-16 04:13:14 +03:00
2008-05-07 18:17:37 +04:00
config CRYPTO_RMD160
2008-07-16 15:28:00 +04:00
tristate "RIPEMD-160 digest algorithm"
2008-11-08 04:18:51 +03:00
select CRYPTO_HASH
2008-07-16 15:28:00 +04:00
help
RIPEMD-160 (ISO/IEC 10118-3:2004).
2008-05-07 18:17:37 +04:00
2008-07-16 15:28:00 +04:00
RIPEMD-160 is a 160-bit cryptographic hash function. It is intended
to be used as a secure replacement for the 128-bit hash functions
2022-07-15 04:59:14 +03:00
MD4, MD5 and its predecessor RIPEMD
2008-07-16 15:28:00 +04:00
(not to be confused with RIPEMD-128).
2008-05-07 18:17:37 +04:00
2008-07-16 15:28:00 +04:00
It's speed is comparable to SHA1 and there are no known attacks
against RIPEMD-160.
2008-05-09 17:30:27 +04:00
2008-07-16 15:28:00 +04:00
Developed by Hans Dobbertin, Antoon Bosselaers and Bart Preneel.
2020-07-19 19:49:59 +03:00
See <https://homes.esat.kuleuven.be/~bosselae/ripemd160.html>
2008-05-09 17:30:27 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_SHA1
tristate "SHA1 digest algorithm"
2008-12-02 16:08:20 +03:00
select CRYPTO_HASH
2022-07-10 00:18:49 +03:00
select CRYPTO_LIB_SHA1
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_SHA256
tristate "SHA224 and SHA256 digest algorithm"
2008-12-03 14:57:49 +03:00
select CRYPTO_HASH
2019-08-17 17:24:35 +03:00
select CRYPTO_LIB_SHA256
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
SHA256 secure hash standard (DFIPS 180-2).
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
This version of SHA implements a 256 bit hash with 128 bits of
security against collision attacks.
2006-06-20 14:37:23 +04:00
2008-07-16 15:28:00 +04:00
This code also includes SHA-224, a 224 bit hash with 112 bits
of security against collision attacks.
2008-04-05 17:04:48 +04:00
config CRYPTO_SHA512
tristate "SHA384 and SHA512 digest algorithms"
2008-12-17 08:49:02 +03:00
select CRYPTO_HASH
2006-06-20 14:59:16 +04:00
help
2008-04-05 17:04:48 +04:00
SHA512 secure hash standard (DFIPS 180-2).
2006-06-20 14:59:16 +04:00
2008-04-05 17:04:48 +04:00
This version of SHA implements a 512 bit hash with 256 bits of
security against collision attacks.
2006-06-20 14:59:16 +04:00
2008-04-05 17:04:48 +04:00
This code also includes SHA-384, a 384 bit hash with 192 bits
of security against collision attacks.
2006-06-20 14:59:16 +04:00
2016-06-17 08:00:35 +03:00
config CRYPTO_SHA3
tristate "SHA3 digest algorithm"
select CRYPTO_HASH
help
SHA-3 secure hash standard (DFIPS 202). It's based on
cryptographic sponge function family called Keccak.
References:
http://keccak.noekeon.org/
2017-08-21 13:51:28 +03:00
config CRYPTO_SM3
2022-03-14 06:11:01 +03:00
tristate
config CRYPTO_SM3_GENERIC
2017-08-21 13:51:28 +03:00
tristate "SM3 digest algorithm"
select CRYPTO_HASH
2022-03-14 06:11:01 +03:00
select CRYPTO_SM3
2017-08-21 13:51:28 +03:00
help
SM3 secure hash function as defined by OSCCA GM/T 0004-2012 SM3).
It is part of the Chinese Commercial Cryptography suite.
References:
http://www.oscca.gov.cn/UpFile/20101222141857786.pdf
https://datatracker.ietf.org/doc/html/draft-shen-sm3-hash
2018-11-07 00:00:01 +03:00
config CRYPTO_STREEBOG
tristate "Streebog Hash Function"
select CRYPTO_HASH
help
Streebog Hash Function (GOST R 34.11-2012, RFC 6986) is one of the Russian
cryptographic standard algorithms (called GOST algorithms).
This setting enables two hash algorithms with 256 and 512 bits output.
References:
https://tc26.ru/upload/iblock/fed/feddbb4d26b685903faa2ba11aea43f6.pdf
https://tools.ietf.org/html/rfc6986
2008-04-05 17:04:48 +04:00
config CRYPTO_WP512
tristate "Whirlpool digest algorithms"
2008-12-07 14:34:37 +03:00
select CRYPTO_HASH
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
Whirlpool hash algorithm 512, 384 and 256-bit hashes
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
Whirlpool-512 is part of the NESSIE cryptographic primitives.
Whirlpool will be part of the ISO/IEC 10118-3:2003(E) standard
2005-04-17 02:20:36 +04:00
See also:
2010-09-12 06:42:47 +04:00
<http://www.larc.usp.br/~pbarreto/WhirlpoolPage.html>
2008-04-05 17:04:48 +04:00
comment "Ciphers"
2005-04-17 02:20:36 +04:00
config CRYPTO_AES
tristate "AES cipher algorithms"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2019-07-02 22:41:33 +03:00
select CRYPTO_LIB_AES
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
AES cipher algorithms (FIPS-197). AES uses the Rijndael
2005-04-17 02:20:36 +04:00
algorithm.
Rijndael appears to be consistently a very good performer in
2008-04-05 17:04:48 +04:00
both hardware and software across a wide range of computing
environments regardless of its use in feedback or non-feedback
modes. Its key setup time is excellent, and its key agility is
good. Rijndael's very low memory requirements make it very well
suited for restricted-space environments, in which it also
demonstrates excellent performance. Rijndael's operations are
among the easiest to defend against power and timing attacks.
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
The AES specifies three key sizes: 128, 192 and 256 bits
2005-04-17 02:20:36 +04:00
See <http://csrc.nist.gov/CryptoToolkit/aes/> for more information.
crypto: aes - add generic time invariant AES cipher
Lookup table based AES is sensitive to timing attacks, which is due to
the fact that such table lookups are data dependent, and the fact that
8 KB worth of tables covers a significant number of cachelines on any
architecture, resulting in an exploitable correlation between the key
and the processing time for known plaintexts.
For network facing algorithms such as CTR, CCM or GCM, this presents a
security risk, which is why arch specific AES ports are typically time
invariant, either through the use of special instructions, or by using
SIMD algorithms that don't rely on table lookups.
For generic code, this is difficult to achieve without losing too much
performance, but we can improve the situation significantly by switching
to an implementation that only needs 256 bytes of table data (the actual
S-box itself), which can be prefetched at the start of each block to
eliminate data dependent latencies.
This code encrypts at ~25 cycles per byte on ARM Cortex-A57 (while the
ordinary generic AES driver manages 18 cycles per byte on this
hardware). Decryption is substantially slower.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-02-02 19:37:40 +03:00
config CRYPTO_AES_TI
tristate "Fixed time AES cipher"
select CRYPTO_ALGAPI
2019-07-02 22:41:22 +03:00
select CRYPTO_LIB_AES
crypto: aes - add generic time invariant AES cipher
Lookup table based AES is sensitive to timing attacks, which is due to
the fact that such table lookups are data dependent, and the fact that
8 KB worth of tables covers a significant number of cachelines on any
architecture, resulting in an exploitable correlation between the key
and the processing time for known plaintexts.
For network facing algorithms such as CTR, CCM or GCM, this presents a
security risk, which is why arch specific AES ports are typically time
invariant, either through the use of special instructions, or by using
SIMD algorithms that don't rely on table lookups.
For generic code, this is difficult to achieve without losing too much
performance, but we can improve the situation significantly by switching
to an implementation that only needs 256 bytes of table data (the actual
S-box itself), which can be prefetched at the start of each block to
eliminate data dependent latencies.
This code encrypts at ~25 cycles per byte on ARM Cortex-A57 (while the
ordinary generic AES driver manages 18 cycles per byte on this
hardware). Decryption is substantially slower.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-02-02 19:37:40 +03:00
help
This is a generic implementation of AES that attempts to eliminate
data dependent latencies as much as possible without affecting
performance too much. It is intended for use by the generic CCM
and GCM drivers, and other CTR or CMAC/XCBC based modes that rely
solely on encryption (although decryption is supported as well, but
with a more dramatic performance hit)
Instead of using 16 lookup tables of 1 KB each, (8 for encryption and
8 for decryption), this implementation only uses just two S-boxes of
256 bytes each, and attempts to eliminate data dependent latencies by
prefetching the entire table into the cache at the start of each
2018-10-18 07:37:58 +03:00
block. Interrupts are also disabled to avoid races where cachelines
are evicted when the CPU is interrupted to do something else.
crypto: aes - add generic time invariant AES cipher
Lookup table based AES is sensitive to timing attacks, which is due to
the fact that such table lookups are data dependent, and the fact that
8 KB worth of tables covers a significant number of cachelines on any
architecture, resulting in an exploitable correlation between the key
and the processing time for known plaintexts.
For network facing algorithms such as CTR, CCM or GCM, this presents a
security risk, which is why arch specific AES ports are typically time
invariant, either through the use of special instructions, or by using
SIMD algorithms that don't rely on table lookups.
For generic code, this is difficult to achieve without losing too much
performance, but we can improve the situation significantly by switching
to an implementation that only needs 256 bytes of table data (the actual
S-box itself), which can be prefetched at the start of each block to
eliminate data dependent latencies.
This code encrypts at ~25 cycles per byte on ARM Cortex-A57 (while the
ordinary generic AES driver manages 18 cycles per byte on this
hardware). Decryption is substantially slower.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-02-02 19:37:40 +03:00
2008-04-05 17:04:48 +04:00
config CRYPTO_ANUBIS
tristate "Anubis cipher algorithm"
2020-09-11 17:11:03 +03:00
depends on CRYPTO_USER_API_ENABLE_OBSOLETE
2008-04-05 17:04:48 +04:00
select CRYPTO_ALGAPI
help
Anubis cipher algorithm.
Anubis is a variable key length cipher which can use keys from
128 bits to 320 bits in length. It was evaluated as a entrant
in the NESSIE competition.
See also:
2010-09-12 06:42:47 +04:00
<https://www.cosic.esat.kuleuven.be/nessie/reports/>
<http://www.larc.usp.br/~pbarreto/AnubisPage.html>
2008-04-05 17:04:48 +04:00
config CRYPTO_ARC4
tristate "ARC4 cipher algorithm"
crypto: arc4 - mark ecb(arc4) skcipher as obsolete
Cryptographic algorithms may have a lifespan that is significantly
shorter than Linux's, and so we need to start phasing out algorithms
that are known to be broken, and are no longer fit for general use.
RC4 (or arc4) is a good example here: there are a few areas where its
use is still somewhat acceptable, e.g., for interoperability with legacy
wifi hardware that can only use WEP or TKIP data encryption, but that
should not imply that, for instance, use of RC4 based EAP-TLS by the WPA
supplicant for negotiating TKIP keys is equally acceptable, or that RC4
should remain available as a general purpose cryptographic transform for
all in-kernel and user space clients.
Now that all in-kernel users that need to retain support have moved to
the arc4 library interface, and the known users of ecb(arc4) via the
socket API (iwd [0] and libell [1][2]) have been updated to switch to a
local implementation, we can take the next step, and mark the ecb(arc4)
skcipher as obsolete, and only provide it if the socket API is enabled in
the first place, as well as provide the option to disable all algorithms
that have been marked as obsolete.
[0] https://git.kernel.org/pub/scm/network/wireless/iwd.git/commit/?id=1db8a85a60c64523
[1] https://git.kernel.org/pub/scm/libs/ell/ell.git/commit/?id=53482ce421b727c2
[2] https://git.kernel.org/pub/scm/libs/ell/ell.git/commit/?id=7f6a137809d42f6b
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-08-31 18:16:49 +03:00
depends on CRYPTO_USER_API_ENABLE_OBSOLETE
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2019-06-12 19:19:53 +03:00
select CRYPTO_LIB_ARC4
2008-04-05 17:04:48 +04:00
help
ARC4 cipher algorithm.
ARC4 is a stream cipher using keys ranging from 8 bits to 2048
bits in length. This algorithm is required for driver-based
WEP, but it should not be for other purposes because of the
weakness of the algorithm.
config CRYPTO_BLOWFISH
tristate "Blowfish cipher algorithm"
select CRYPTO_ALGAPI
2011-09-02 02:45:07 +04:00
select CRYPTO_BLOWFISH_COMMON
2008-04-05 17:04:48 +04:00
help
Blowfish cipher algorithm, by Bruce Schneier.
This is a variable key length cipher which can use keys from 32
bits to 448 bits in length. It's fast, simple and specifically
designed for use on "large microprocessors".
See also:
2020-07-19 19:49:59 +03:00
<https://www.schneier.com/blowfish.html>
2008-04-05 17:04:48 +04:00
2011-09-02 02:45:07 +04:00
config CRYPTO_BLOWFISH_COMMON
tristate
help
Common parts of the Blowfish cipher algorithm shared by the
generic c and the assembler implementations.
See also:
2020-07-19 19:49:59 +03:00
<https://www.schneier.com/blowfish.html>
2011-09-02 02:45:07 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_CAMELLIA
tristate "Camellia cipher algorithms"
select CRYPTO_ALGAPI
help
Camellia cipher algorithms module.
Camellia is a symmetric key block cipher developed jointly
at NTT and Mitsubishi Electric Corporation.
The Camellia specifies three key sizes: 128, 192 and 256 bits.
See also:
<https://info.isl.ntt.co.jp/crypt/eng/camellia/index_s.html>
2012-11-13 13:43:14 +04:00
config CRYPTO_CAST_COMMON
tristate
help
Common parts of the CAST cipher algorithms shared by the
generic c and the assembler implementations.
2005-04-17 02:20:36 +04:00
config CRYPTO_CAST5
tristate "CAST5 (CAST-128) cipher algorithm"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2012-11-13 13:43:14 +04:00
select CRYPTO_CAST_COMMON
2005-04-17 02:20:36 +04:00
help
The CAST5 encryption algorithm (synonymous with CAST-128) is
described in RFC2144.
config CRYPTO_CAST6
tristate "CAST6 (CAST-256) cipher algorithm"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2012-11-13 13:43:14 +04:00
select CRYPTO_CAST_COMMON
2005-04-17 02:20:36 +04:00
help
The CAST6 encryption algorithm (synonymous with CAST-256) is
described in RFC2612.
2008-04-05 17:04:48 +04:00
config CRYPTO_DES
tristate "DES and Triple DES EDE cipher algorithms"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2019-08-15 12:01:09 +03:00
select CRYPTO_LIB_DES
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
2005-09-02 04:42:46 +04:00
2008-04-05 17:04:48 +04:00
config CRYPTO_FCRYPT
tristate "FCrypt cipher algorithm"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
FCrypt algorithm used by RxRPC.
2005-04-17 02:20:36 +04:00
config CRYPTO_KHAZAD
tristate "Khazad cipher algorithm"
2020-09-11 17:11:03 +03:00
depends on CRYPTO_USER_API_ENABLE_OBSOLETE
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
Khazad cipher algorithm.
Khazad was a finalist in the initial NESSIE competition. It is
an algorithm optimized for 64-bit processors with good performance
on 32-bit processors. Khazad uses an 128 bit key size.
See also:
2010-09-12 06:42:47 +04:00
<http://www.larc.usp.br/~pbarreto/KhazadPage.html>
2005-04-17 02:20:36 +04:00
2015-06-01 14:43:56 +03:00
config CRYPTO_CHACHA20
crypto: chacha - add XChaCha12 support
Now that the generic implementation of ChaCha20 has been refactored to
allow varying the number of rounds, add support for XChaCha12, which is
the XSalsa construction applied to ChaCha12. ChaCha12 is one of the
three ciphers specified by the original ChaCha paper
(https://cr.yp.to/chacha/chacha-20080128.pdf: "ChaCha, a variant of
Salsa20"), alongside ChaCha8 and ChaCha20. ChaCha12 is faster than
ChaCha20 but has a lower, but still large, security margin.
We need XChaCha12 support so that it can be used in the Adiantum
encryption mode, which enables disk/file encryption on low-end mobile
devices where AES-XTS is too slow as the CPUs lack AES instructions.
We'd prefer XChaCha20 (the more popular variant), but it's too slow on
some of our target devices, so at least in some cases we do need the
XChaCha12-based version. In more detail, the problem is that Adiantum
is still much slower than we're happy with, and encryption still has a
quite noticeable effect on the feel of low-end devices. Users and
vendors push back hard against encryption that degrades the user
experience, which always risks encryption being disabled entirely. So
we need to choose the fastest option that gives us a solid margin of
security, and here that's XChaCha12. The best known attack on ChaCha
breaks only 7 rounds and has 2^235 time complexity, so ChaCha12's
security margin is still better than AES-256's. Much has been learned
about cryptanalysis of ARX ciphers since Salsa20 was originally designed
in 2005, and it now seems we can be comfortable with a smaller number of
rounds. The eSTREAM project also suggests the 12-round version of
Salsa20 as providing the best balance among the different variants:
combining very good performance with a "comfortable margin of security".
Note that it would be trivial to add vanilla ChaCha12 in addition to
XChaCha12. However, it's unneeded for now and therefore is omitted.
As discussed in the patch that introduced XChaCha20 support, I
considered splitting the code into separate chacha-common, chacha20,
xchacha20, and xchacha12 modules, so that these algorithms could be
enabled/disabled independently. However, since nearly all the code is
shared anyway, I ultimately decided there would have been little benefit
to the added complexity.
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Martin Willi <martin@strongswan.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-17 04:26:22 +03:00
tristate "ChaCha stream cipher algorithms"
2019-11-08 15:22:08 +03:00
select CRYPTO_LIB_CHACHA_GENERIC
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2015-06-01 14:43:56 +03:00
help
crypto: chacha - add XChaCha12 support
Now that the generic implementation of ChaCha20 has been refactored to
allow varying the number of rounds, add support for XChaCha12, which is
the XSalsa construction applied to ChaCha12. ChaCha12 is one of the
three ciphers specified by the original ChaCha paper
(https://cr.yp.to/chacha/chacha-20080128.pdf: "ChaCha, a variant of
Salsa20"), alongside ChaCha8 and ChaCha20. ChaCha12 is faster than
ChaCha20 but has a lower, but still large, security margin.
We need XChaCha12 support so that it can be used in the Adiantum
encryption mode, which enables disk/file encryption on low-end mobile
devices where AES-XTS is too slow as the CPUs lack AES instructions.
We'd prefer XChaCha20 (the more popular variant), but it's too slow on
some of our target devices, so at least in some cases we do need the
XChaCha12-based version. In more detail, the problem is that Adiantum
is still much slower than we're happy with, and encryption still has a
quite noticeable effect on the feel of low-end devices. Users and
vendors push back hard against encryption that degrades the user
experience, which always risks encryption being disabled entirely. So
we need to choose the fastest option that gives us a solid margin of
security, and here that's XChaCha12. The best known attack on ChaCha
breaks only 7 rounds and has 2^235 time complexity, so ChaCha12's
security margin is still better than AES-256's. Much has been learned
about cryptanalysis of ARX ciphers since Salsa20 was originally designed
in 2005, and it now seems we can be comfortable with a smaller number of
rounds. The eSTREAM project also suggests the 12-round version of
Salsa20 as providing the best balance among the different variants:
combining very good performance with a "comfortable margin of security".
Note that it would be trivial to add vanilla ChaCha12 in addition to
XChaCha12. However, it's unneeded for now and therefore is omitted.
As discussed in the patch that introduced XChaCha20 support, I
considered splitting the code into separate chacha-common, chacha20,
xchacha20, and xchacha12 modules, so that these algorithms could be
enabled/disabled independently. However, since nearly all the code is
shared anyway, I ultimately decided there would have been little benefit
to the added complexity.
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Martin Willi <martin@strongswan.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-17 04:26:22 +03:00
The ChaCha20, XChaCha20, and XChaCha12 stream cipher algorithms.
2015-06-01 14:43:56 +03:00
ChaCha20 is a 256-bit high-speed stream cipher designed by Daniel J.
Bernstein and further specified in RFC7539 for use in IETF protocols.
crypto: chacha20-generic - add XChaCha20 support
Add support for the XChaCha20 stream cipher. XChaCha20 is the
application of the XSalsa20 construction
(https://cr.yp.to/snuffle/xsalsa-20081128.pdf) to ChaCha20 rather than
to Salsa20. XChaCha20 extends ChaCha20's nonce length from 64 bits (or
96 bits, depending on convention) to 192 bits, while provably retaining
ChaCha20's security. XChaCha20 uses the ChaCha20 permutation to map the
key and first 128 nonce bits to a 256-bit subkey. Then, it does the
ChaCha20 stream cipher with the subkey and remaining 64 bits of nonce.
We need XChaCha support in order to add support for the Adiantum
encryption mode. Note that to meet our performance requirements, we
actually plan to primarily use the variant XChaCha12. But we believe
it's wise to first add XChaCha20 as a baseline with a higher security
margin, in case there are any situations where it can be used.
Supporting both variants is straightforward.
Since XChaCha20's subkey differs for each request, XChaCha20 can't be a
template that wraps ChaCha20; that would require re-keying the
underlying ChaCha20 for every request, which wouldn't be thread-safe.
Instead, we make XChaCha20 its own top-level algorithm which calls the
ChaCha20 streaming implementation internally.
Similar to the existing ChaCha20 implementation, we define the IV to be
the nonce and stream position concatenated together. This allows users
to seek to any position in the stream.
I considered splitting the code into separate chacha20-common, chacha20,
and xchacha20 modules, so that chacha20 and xchacha20 could be
enabled/disabled independently. However, since nearly all the code is
shared anyway, I ultimately decided there would have been little benefit
to the added complexity of separate modules.
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Martin Willi <martin@strongswan.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-17 04:26:20 +03:00
This is the portable C implementation of ChaCha20. See also:
2020-07-19 19:49:59 +03:00
<https://cr.yp.to/chacha/chacha-20080128.pdf>
2015-06-01 14:43:56 +03:00
crypto: chacha20-generic - add XChaCha20 support
Add support for the XChaCha20 stream cipher. XChaCha20 is the
application of the XSalsa20 construction
(https://cr.yp.to/snuffle/xsalsa-20081128.pdf) to ChaCha20 rather than
to Salsa20. XChaCha20 extends ChaCha20's nonce length from 64 bits (or
96 bits, depending on convention) to 192 bits, while provably retaining
ChaCha20's security. XChaCha20 uses the ChaCha20 permutation to map the
key and first 128 nonce bits to a 256-bit subkey. Then, it does the
ChaCha20 stream cipher with the subkey and remaining 64 bits of nonce.
We need XChaCha support in order to add support for the Adiantum
encryption mode. Note that to meet our performance requirements, we
actually plan to primarily use the variant XChaCha12. But we believe
it's wise to first add XChaCha20 as a baseline with a higher security
margin, in case there are any situations where it can be used.
Supporting both variants is straightforward.
Since XChaCha20's subkey differs for each request, XChaCha20 can't be a
template that wraps ChaCha20; that would require re-keying the
underlying ChaCha20 for every request, which wouldn't be thread-safe.
Instead, we make XChaCha20 its own top-level algorithm which calls the
ChaCha20 streaming implementation internally.
Similar to the existing ChaCha20 implementation, we define the IV to be
the nonce and stream position concatenated together. This allows users
to seek to any position in the stream.
I considered splitting the code into separate chacha20-common, chacha20,
and xchacha20 modules, so that chacha20 and xchacha20 could be
enabled/disabled independently. However, since nearly all the code is
shared anyway, I ultimately decided there would have been little benefit
to the added complexity of separate modules.
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Martin Willi <martin@strongswan.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-17 04:26:20 +03:00
XChaCha20 is the application of the XSalsa20 construction to ChaCha20
rather than to Salsa20. XChaCha20 extends ChaCha20's nonce length
from 64 bits (or 96 bits using the RFC7539 convention) to 192 bits,
while provably retaining ChaCha20's security. See also:
<https://cr.yp.to/snuffle/xsalsa-20081128.pdf>
crypto: chacha - add XChaCha12 support
Now that the generic implementation of ChaCha20 has been refactored to
allow varying the number of rounds, add support for XChaCha12, which is
the XSalsa construction applied to ChaCha12. ChaCha12 is one of the
three ciphers specified by the original ChaCha paper
(https://cr.yp.to/chacha/chacha-20080128.pdf: "ChaCha, a variant of
Salsa20"), alongside ChaCha8 and ChaCha20. ChaCha12 is faster than
ChaCha20 but has a lower, but still large, security margin.
We need XChaCha12 support so that it can be used in the Adiantum
encryption mode, which enables disk/file encryption on low-end mobile
devices where AES-XTS is too slow as the CPUs lack AES instructions.
We'd prefer XChaCha20 (the more popular variant), but it's too slow on
some of our target devices, so at least in some cases we do need the
XChaCha12-based version. In more detail, the problem is that Adiantum
is still much slower than we're happy with, and encryption still has a
quite noticeable effect on the feel of low-end devices. Users and
vendors push back hard against encryption that degrades the user
experience, which always risks encryption being disabled entirely. So
we need to choose the fastest option that gives us a solid margin of
security, and here that's XChaCha12. The best known attack on ChaCha
breaks only 7 rounds and has 2^235 time complexity, so ChaCha12's
security margin is still better than AES-256's. Much has been learned
about cryptanalysis of ARX ciphers since Salsa20 was originally designed
in 2005, and it now seems we can be comfortable with a smaller number of
rounds. The eSTREAM project also suggests the 12-round version of
Salsa20 as providing the best balance among the different variants:
combining very good performance with a "comfortable margin of security".
Note that it would be trivial to add vanilla ChaCha12 in addition to
XChaCha12. However, it's unneeded for now and therefore is omitted.
As discussed in the patch that introduced XChaCha20 support, I
considered splitting the code into separate chacha-common, chacha20,
xchacha20, and xchacha12 modules, so that these algorithms could be
enabled/disabled independently. However, since nearly all the code is
shared anyway, I ultimately decided there would have been little benefit
to the added complexity.
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Martin Willi <martin@strongswan.org>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2018-11-17 04:26:22 +03:00
XChaCha12 is XChaCha20 reduced to 12 rounds, with correspondingly
reduced security margin but increased performance. It can be needed
in some performance-sensitive scenarios.
2008-04-05 17:04:48 +04:00
config CRYPTO_SEED
tristate "SEED cipher algorithm"
2020-09-11 17:11:03 +03:00
depends on CRYPTO_USER_API_ENABLE_OBSOLETE
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
SEED cipher algorithm (RFC4269).
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
SEED is a 128-bit symmetric key block cipher that has been
developed by KISA (Korea Information Security Agency) as a
national standard encryption algorithm of the Republic of Korea.
It is a 16 round block cipher with the key size of 128 bit.
See also:
<http://www.kisa.or.kr/kisa/seed/jsp/seed_eng.jsp>
2022-07-04 12:42:48 +03:00
config CRYPTO_ARIA
tristate "ARIA cipher algorithm"
select CRYPTO_ALGAPI
help
ARIA cipher algorithm (RFC5794).
ARIA is a standard encryption algorithm of the Republic of Korea.
The ARIA specifies three key sizes and rounds.
128-bit: 12 rounds.
192-bit: 14 rounds.
256-bit: 16 rounds.
See also:
<https://seed.kisa.or.kr/kisa/algorithm/EgovAriaInfo.do>
2008-04-05 17:04:48 +04:00
config CRYPTO_SERPENT
tristate "Serpent cipher algorithm"
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
Serpent cipher algorithm, by Anderson, Biham & Knudsen.
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
Keys are allowed to be from 0 to 256 bits in length, in steps
2021-02-01 21:02:30 +03:00
of 8 bits.
2008-04-05 17:04:48 +04:00
See also:
2020-07-19 19:49:59 +03:00
<https://www.cl.cam.ac.uk/~rja14/serpent.html>
2008-04-05 17:04:48 +04:00
2018-03-06 12:44:42 +03:00
config CRYPTO_SM4
2022-03-14 06:11:01 +03:00
tristate
config CRYPTO_SM4_GENERIC
2018-03-06 12:44:42 +03:00
tristate "SM4 cipher algorithm"
select CRYPTO_ALGAPI
2022-03-14 06:11:01 +03:00
select CRYPTO_SM4
2018-03-06 12:44:42 +03:00
help
SM4 cipher algorithms (OSCCA GB/T 32907-2016).
SM4 (GBT.32907-2016) is a cryptographic standard issued by the
Organization of State Commercial Administration of China (OSCCA)
as an authorized cryptographic algorithms for the use within China.
SMS4 was originally created for use in protecting wireless
networks, and is mandated in the Chinese National Standard for
Wireless LAN WAPI (Wired Authentication and Privacy Infrastructure)
(GB.15629.11-2003).
The latest SM4 standard (GBT.32907-2016) was proposed by OSCCA and
standardized through TC 260 of the Standardization Administration
of the People's Republic of China (SAC).
The input, output, and key of SMS4 are each 128 bits.
See also: <https://eprint.iacr.org/2008/329.pdf>
If unsure, say N.
2008-04-05 17:04:48 +04:00
config CRYPTO_TEA
tristate "TEA, XTEA and XETA cipher algorithms"
2020-09-11 17:11:03 +03:00
depends on CRYPTO_USER_API_ENABLE_OBSOLETE
2006-08-21 15:08:13 +04:00
select CRYPTO_ALGAPI
2005-04-17 02:20:36 +04:00
help
2008-04-05 17:04:48 +04:00
TEA cipher algorithm.
2005-04-17 02:20:36 +04:00
2008-04-05 17:04:48 +04:00
Tiny Encryption Algorithm is a simple cipher that uses
many rounds for security. It is very fast and uses
little memory.
Xtendend Tiny Encryption Algorithm is a modification to
the TEA algorithm to address a potential key weakness
in the TEA algorithm.
Xtendend Encryption Tiny Algorithm is a mis-implementation
of the XTEA algorithm for compatibility purposes.
config CRYPTO_TWOFISH
tristate "Twofish cipher algorithm"
2006-10-22 08:49:17 +04:00
select CRYPTO_ALGAPI
2008-04-05 17:04:48 +04:00
select CRYPTO_TWOFISH_COMMON
2006-10-22 08:49:17 +04:00
help
2008-04-05 17:04:48 +04:00
Twofish cipher algorithm.
2006-10-22 08:49:17 +04:00
2008-04-05 17:04:48 +04:00
Twofish was submitted as an AES (Advanced Encryption Standard)
candidate cipher by researchers at CounterPane Systems. It is a
16 round block cipher supporting key sizes of 128, 192, and 256
bits.
2006-10-22 08:49:17 +04:00
2008-04-05 17:04:48 +04:00
See also:
2020-07-19 19:49:59 +03:00
<https://www.schneier.com/twofish.html>
2008-04-05 17:04:48 +04:00
config CRYPTO_TWOFISH_COMMON
tristate
help
Common parts of the Twofish cipher algorithm shared by the
generic c and the assembler implementations.
comment "Compression"
config CRYPTO_DEFLATE
tristate "Deflate compression algorithm"
select CRYPTO_ALGAPI
2016-10-21 15:19:53 +03:00
select CRYPTO_ACOMP2
2008-04-05 17:04:48 +04:00
select ZLIB_INFLATE
select ZLIB_DEFLATE
[CRYPTO] aead: Add authenc
This patch adds the authenc algorithm which constructs an AEAD algorithm
from an asynchronous block cipher and a hash. The construction is done
by concatenating the encrypted result from the cipher with the output
from the hash, as is used by the IPsec ESP protocol.
The authenc algorithm exists as a template with four parameters:
authenc(auth, authsize, enc, enckeylen).
The authentication algorithm, the authentication size (i.e., truncating
the output of the authentication algorithm), the encryption algorithm,
and the encryption key length. Both the size field and the key length
field are in bytes. For example, AES-128 with SHA1-HMAC would be
represented by
authenc(hmac(sha1), 12, cbc(aes), 16)
The key for the authenc algorithm is the concatenation of the keys for
the authentication algorithm with the encryption algorithm. For the
above example, if a key of length 36 bytes is given, then hmac(sha1)
would receive the first 20 bytes while the last 16 would be given to
cbc(aes).
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-08-30 12:24:15 +04:00
help
2008-04-05 17:04:48 +04:00
This is the Deflate algorithm (RFC1951), specified for use in
IPSec with the IPCOMP protocol (RFC3173, RFC2394).
You will most probably want this if using IPSec.
[CRYPTO] aead: Add authenc
This patch adds the authenc algorithm which constructs an AEAD algorithm
from an asynchronous block cipher and a hash. The construction is done
by concatenating the encrypted result from the cipher with the output
from the hash, as is used by the IPsec ESP protocol.
The authenc algorithm exists as a template with four parameters:
authenc(auth, authsize, enc, enckeylen).
The authentication algorithm, the authentication size (i.e., truncating
the output of the authentication algorithm), the encryption algorithm,
and the encryption key length. Both the size field and the key length
field are in bytes. For example, AES-128 with SHA1-HMAC would be
represented by
authenc(hmac(sha1), 12, cbc(aes), 16)
The key for the authenc algorithm is the concatenation of the keys for
the authentication algorithm with the encryption algorithm. For the
above example, if a key of length 36 bytes is given, then hmac(sha1)
would receive the first 20 bytes while the last 16 would be given to
cbc(aes).
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-08-30 12:24:15 +04:00
2007-12-07 11:53:23 +03:00
config CRYPTO_LZO
tristate "LZO compression algorithm"
select CRYPTO_ALGAPI
2016-10-21 15:19:49 +03:00
select CRYPTO_ACOMP2
2007-12-07 11:53:23 +03:00
select LZO_COMPRESS
select LZO_DECOMPRESS
help
This is the LZO algorithm.
2012-07-19 18:42:41 +04:00
config CRYPTO_842
tristate "842 compression algorithm"
2015-05-07 20:49:15 +03:00
select CRYPTO_ALGAPI
2016-10-21 15:19:52 +03:00
select CRYPTO_ACOMP2
2015-05-07 20:49:15 +03:00
select 842_COMPRESS
select 842_DECOMPRESS
2012-07-19 18:42:41 +04:00
help
This is the 842 algorithm.
2013-07-09 03:01:51 +04:00
config CRYPTO_LZ4
tristate "LZ4 compression algorithm"
select CRYPTO_ALGAPI
2016-10-21 15:19:50 +03:00
select CRYPTO_ACOMP2
2013-07-09 03:01:51 +04:00
select LZ4_COMPRESS
select LZ4_DECOMPRESS
help
This is the LZ4 algorithm.
config CRYPTO_LZ4HC
tristate "LZ4HC compression algorithm"
select CRYPTO_ALGAPI
2016-10-21 15:19:51 +03:00
select CRYPTO_ACOMP2
2013-07-09 03:01:51 +04:00
select LZ4HC_COMPRESS
select LZ4_DECOMPRESS
help
This is the LZ4 high compression mode algorithm.
2012-07-19 18:42:41 +04:00
2018-03-30 22:14:53 +03:00
config CRYPTO_ZSTD
tristate "Zstd compression algorithm"
select CRYPTO_ALGAPI
select CRYPTO_ACOMP2
select ZSTD_COMPRESS
select ZSTD_DECOMPRESS
help
This is the zstd algorithm.
2008-08-14 16:15:52 +04:00
comment "Random Number Generation"
config CRYPTO_ANSI_CPRNG
tristate "Pseudo Random Number Generation for Cryptographic modules"
select CRYPTO_AES
select CRYPTO_RNG
help
This option enables the generic pseudo random number generator
for cryptographic modules. Uses the Algorithm specified in
2010-01-27 03:00:10 +03:00
ANSI X9.31 A.2.4. Note that this option must be enabled if
CRYPTO_FIPS is selected
2008-08-14 16:15:52 +04:00
2014-07-04 18:15:08 +04:00
menuconfig CRYPTO_DRBG_MENU
2014-05-31 19:22:31 +04:00
tristate "NIST SP800-90A DRBG"
help
NIST SP800-90A compliant DRBG. In the following submenu, one or
more of the DRBG types must be selected.
2014-07-04 18:15:08 +04:00
if CRYPTO_DRBG_MENU
2014-05-31 19:22:31 +04:00
config CRYPTO_DRBG_HMAC
2015-06-03 09:49:31 +03:00
bool
2014-05-31 19:22:31 +04:00
default y
select CRYPTO_HMAC
2021-06-30 13:32:52 +03:00
select CRYPTO_SHA512
2014-05-31 19:22:31 +04:00
config CRYPTO_DRBG_HASH
bool "Enable Hash DRBG"
2015-06-11 03:55:10 +03:00
select CRYPTO_SHA256
2014-05-31 19:22:31 +04:00
help
Enable the Hash DRBG variant as defined in NIST SP800-90A.
config CRYPTO_DRBG_CTR
bool "Enable CTR DRBG"
select CRYPTO_AES
2020-04-24 16:40:47 +03:00
select CRYPTO_CTR
2014-05-31 19:22:31 +04:00
help
Enable the CTR DRBG variant as defined in NIST SP800-90A.
2014-07-04 18:15:08 +04:00
config CRYPTO_DRBG
tristate
2015-06-03 09:49:31 +03:00
default CRYPTO_DRBG_MENU
2014-07-04 18:15:08 +04:00
select CRYPTO_RNG
2015-05-25 16:10:20 +03:00
select CRYPTO_JITTERENTROPY
2014-07-04 18:15:08 +04:00
endif # if CRYPTO_DRBG_MENU
2014-05-31 19:22:31 +04:00
2015-05-25 16:10:20 +03:00
config CRYPTO_JITTERENTROPY
tristate "Jitterentropy Non-Deterministic Random Number Generator"
2016-01-26 16:47:10 +03:00
select CRYPTO_RNG
2015-05-25 16:10:20 +03:00
help
The Jitterentropy RNG is a noise that is intended
to provide seed to another RNG. The RNG does not
perform any cryptographic whitening of the generated
random numbers. This Jitterentropy RNG registers with
the kernel crypto API and can be used by any caller.
2021-11-19 09:55:58 +03:00
config CRYPTO_KDF800108_CTR
tristate
2022-01-18 08:31:29 +03:00
select CRYPTO_HMAC
2021-12-21 22:31:42 +03:00
select CRYPTO_SHA256
2021-11-19 09:55:58 +03:00
2010-10-19 17:12:39 +04:00
config CRYPTO_USER_API
tristate
2010-10-19 17:23:00 +04:00
config CRYPTO_USER_API_HASH
tristate "User-space interface for hash algorithms"
2010-11-29 17:56:03 +03:00
depends on NET
2010-10-19 17:23:00 +04:00
select CRYPTO_HASH
select CRYPTO_USER_API
help
This option enables the user-spaces interface for hash
algorithms.
2010-10-19 17:31:55 +04:00
config CRYPTO_USER_API_SKCIPHER
tristate "User-space interface for symmetric key cipher algorithms"
2010-11-29 17:56:03 +03:00
depends on NET
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2010-10-19 17:31:55 +04:00
select CRYPTO_USER_API
help
This option enables the user-spaces interface for symmetric
key cipher algorithms.
2014-12-26 01:00:39 +03:00
config CRYPTO_USER_API_RNG
tristate "User-space interface for random number generator algorithms"
depends on NET
select CRYPTO_RNG
select CRYPTO_USER_API
help
This option enables the user-spaces interface for random
number generator algorithms.
2020-09-18 18:42:16 +03:00
config CRYPTO_USER_API_RNG_CAVP
bool "Enable CAVP testing of DRBG"
depends on CRYPTO_USER_API_RNG && CRYPTO_DRBG
help
This option enables extra API for CAVP testing via the user-space
interface: resetting of DRBG entropy, and providing Additional Data.
This should only be enabled for CAVP testing. You should say
no unless you know what this is.
2015-05-28 06:30:35 +03:00
config CRYPTO_USER_API_AEAD
tristate "User-space interface for AEAD cipher algorithms"
depends on NET
select CRYPTO_AEAD
2019-10-25 22:41:13 +03:00
select CRYPTO_SKCIPHER
2017-07-30 15:32:58 +03:00
select CRYPTO_NULL
2015-05-28 06:30:35 +03:00
select CRYPTO_USER_API
help
This option enables the user-spaces interface for AEAD
cipher algorithms.
crypto: arc4 - mark ecb(arc4) skcipher as obsolete
Cryptographic algorithms may have a lifespan that is significantly
shorter than Linux's, and so we need to start phasing out algorithms
that are known to be broken, and are no longer fit for general use.
RC4 (or arc4) is a good example here: there are a few areas where its
use is still somewhat acceptable, e.g., for interoperability with legacy
wifi hardware that can only use WEP or TKIP data encryption, but that
should not imply that, for instance, use of RC4 based EAP-TLS by the WPA
supplicant for negotiating TKIP keys is equally acceptable, or that RC4
should remain available as a general purpose cryptographic transform for
all in-kernel and user space clients.
Now that all in-kernel users that need to retain support have moved to
the arc4 library interface, and the known users of ecb(arc4) via the
socket API (iwd [0] and libell [1][2]) have been updated to switch to a
local implementation, we can take the next step, and mark the ecb(arc4)
skcipher as obsolete, and only provide it if the socket API is enabled in
the first place, as well as provide the option to disable all algorithms
that have been marked as obsolete.
[0] https://git.kernel.org/pub/scm/network/wireless/iwd.git/commit/?id=1db8a85a60c64523
[1] https://git.kernel.org/pub/scm/libs/ell/ell.git/commit/?id=53482ce421b727c2
[2] https://git.kernel.org/pub/scm/libs/ell/ell.git/commit/?id=7f6a137809d42f6b
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-08-31 18:16:49 +03:00
config CRYPTO_USER_API_ENABLE_OBSOLETE
bool "Enable obsolete cryptographic algorithms for userspace"
depends on CRYPTO_USER_API
default y
help
Allow obsolete cryptographic algorithms to be selected that have
already been phased out from internal use by the kernel, and are
only useful for userspace clients that still rely on them.
2018-09-19 13:10:54 +03:00
config CRYPTO_STATS
bool "Crypto usage statistics for User-space"
2018-11-29 17:42:17 +03:00
depends on CRYPTO_USER
2018-09-19 13:10:54 +03:00
help
This option enables the gathering of crypto stats.
This will collect:
- encrypt/decrypt size and numbers of symmeric operations
- compress/decompress size and numbers of compress operations
- size and numbers of hash operations
- encrypt/decrypt/sign/verify numbers for asymmetric operations
- generate/seed numbers for rng operations
2013-05-06 16:40:01 +04:00
config CRYPTO_HASH_INFO
bool
2022-08-20 21:41:41 +03:00
if ARM
source "arch/arm/crypto/Kconfig"
endif
if ARM64
source "arch/arm64/crypto/Kconfig"
endif
2022-08-20 21:41:35 +03:00
if MIPS
source "arch/mips/crypto/Kconfig"
endif
2022-08-20 21:41:36 +03:00
if PPC
source "arch/powerpc/crypto/Kconfig"
endif
2022-08-20 21:41:37 +03:00
if S390
source "arch/s390/crypto/Kconfig"
endif
2022-08-20 21:41:38 +03:00
if SPARC
source "arch/sparc/crypto/Kconfig"
endif
2022-08-20 21:41:39 +03:00
if X86
source "arch/x86/crypto/Kconfig"
endif
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source "drivers/crypto/Kconfig"
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source "crypto/asymmetric_keys/Kconfig"
source "certs/Kconfig"
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endif # if CRYPTO
