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Merge patch series "Add Huashan Pi board support"

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Inochi Amaoto <inochiama@outlook.com> says:

Huashan Pi board is an embedded development platform based on the
CV1812H chip. Add minimal device tree files for this board.
Currently, it can boot to a basic shell.

NOTE: this series is based on the Jisheng's Milk-V Duo patch.

Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html
Link: https://lore.kernel.org/linux-riscv/20231006121449.721-1-jszhang@kernel.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Conor Dooley 2023-11-30 12:40:38 +00:00
commit 637cb4b61b
8 changed files with 281 additions and 114 deletions
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1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@ -66,6 +66,7 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- sophgo,cv1800b-plic
- sophgo,cv1812h-plic
- sophgo,sg2042-plic
- thead,th1520-plic
- const: thead,c900-plic

4
Documentation/devicetree/bindings/riscv/sophgo.yaml
View File

@ -22,6 +22,10 @@ properties:
- enum:
- milkv,duo
- const: sophgo,cv1800b
- items:
- enum:
- sophgo,huashan-pi
- const: sophgo,cv1812h
- items:
- enum:
- milkv,pioneer

1
Documentation/devicetree/bindings/timer/sifive,clint.yaml
View File

@ -38,6 +38,7 @@ properties:
- enum:
- allwinner,sun20i-d1-clint
- sophgo,cv1800b-clint
- sophgo,cv1812h-clint
- thead,th1520-clint
- const: thead,c900-clint
- items:

1
arch/riscv/boot/dts/sophgo/Makefile
View File

@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb

123
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
View File

@ -3,121 +3,16 @@
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "cv18xx.dtsi"
/ {
compatible = "sophgo,cv1800b";
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
dma-noncoherent;
ranges;
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
plic: interrupt-controller@70000000 {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};
&plic {
compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};

48
arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts Normal file
View File

@ -0,0 +1,48 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
/dts-v1/;
#include "cv1812h.dtsi"
/ {
model = "Huashan Pi";
compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
coprocessor_rtos: region@8fe00000 {
reg = <0x8fe00000 0x200000>;
no-map;
};
};
};
&osc {
clock-frequency = <25000000>;
};
&uart0 {
status = "okay";
};

24
arch/riscv/boot/dts/sophgo/cv1812h.dtsi Normal file
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@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "cv18xx.dtsi"
/ {
compatible = "sophgo,cv1812h";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
&plic {
compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
};

193
arch/riscv/boot/dts/sophgo/cv18xx.dtsi Normal file
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@ -0,0 +1,193 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <25000000>;
cpu0: cpu@0 {
compatible = "thead,c906", "riscv";
device_type = "cpu";
reg = <0>;
d-cache-block-size = <64>;
d-cache-sets = <512>;
d-cache-size = <65536>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
mmu-type = "riscv,sv39";
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
"zifencei", "zihpm";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
};
osc: oscillator {
compatible = "fixed-clock";
clock-output-names = "osc_25m";
#clock-cells = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <1>;
#size-cells = <1>;
dma-noncoherent;
ranges;
gpio0: gpio@3020000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio1: gpio@3021000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3021000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio2: gpio@3022000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3022000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
};
};
gpio3: gpio@3023000 {
compatible = "snps,dw-apb-gpio";
reg = <0x3023000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
portd: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
};
};
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: serial@4150000 {
compatible = "snps,dw-apb-uart";
reg = <0x04150000 0x100>;
interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart2: serial@4160000 {
compatible = "snps,dw-apb-uart";
reg = <0x04160000 0x100>;
interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart3: serial@4170000 {
compatible = "snps,dw-apb-uart";
reg = <0x04170000 0x100>;
interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart4: serial@41c0000 {
compatible = "snps,dw-apb-uart";
reg = <0x041c0000 0x100>;
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
plic: interrupt-controller@70000000 {
reg = <0x70000000 0x4000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <101>;
};
clint: timer@74000000 {
reg = <0x74000000 0x10000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
};
};