iv/linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

TI K3 device tree updates for v6.8

Browse Source 
New features across K3 SoCs:
 - ov5640 and imx219 sensor overlays added to various am62x/am62a boards.
 - TP6594 and family support for J7200, j721s2,j721e, am69/j784s4 boards
 
 Generic Fixes:
 - minor white space cleanups
 - Addition of optional regs for more complete DMA description across all K3
   SoCs.
 
 Misc:
 - chip_id node moves under wkup_conf bus.
 - COMPILE_TEST+OF_ALL_DTBS is now standard usage for testing overlays.
 
 SoC specific Fixes/Features:
 AM62A
  - gpio pin count fixups.
 AM625
  - Adds verdin am62x-mallow board
  - Adds IMG's AXE-RGX GPU support
  - Adds gpio-ranges support for main domain GPIOs.
  - SK now defaults to mcu gpio marked as reserved to cater to MCU use cases
 AM64
  - EVM/SK now defaults to mcu gpio marked as reserved to cater to MCU use cases
 AM65
  - Fix for DSS Irq trigger type, proper fixup for dss-oldi-io-ctrl node
  - misc splitup to make AM652 device variant reusable
 J7200
  - mmc: itap delay fixups for DDR52
 J721S2/AM68
  - mmc: itap delay fixups for DDR50
 J784S4/AM69
  - mmc: itap delay fixups for DDR50
 
 Board specific fixes/Features:
 - iot2050 cleanups for enabling icssg-prueth nodes, runtime pinmuxing,
   dropping ecap0pwm nodes, misc cleanups.
 - am62x-verdin adds uart2, minor fixups for spi1 chip-select pinctrl
 - am62-phycore adds hdmi support
 - am64-phycore adds R5F support.
 - am62x-beagleplay renames console uart pinmuxes.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE+KKGk1TrgjIXoxo03bWEnRc2JJ0FAmWAXs8ACgkQ3bWEnRc2
 JJ2cvBAAiY8RLIg8ZKvLrr6lNlmGBilAD/tg8K9/dbx1R/xMrCZZYcVZI84tkK8q
 zka9Z7xs71ZMhR+3+mnmIydIG0QSMp+R38s6O/bQnNmj2WAhmb94a6kTnWBsiNO3
 Ji097mVY7b4L4CNmQ+wEfcirX3bJdGqKeHXRoV2fk/1ZBCmQw5aquRxbXA9e1txm
 MOeFrOomaB6h5ZYVEpWsv8em/IPnbhaFqlbsd8NWrVq/rvS4ZQvWawKALJau5ruX
 zRv3RijeoajJkndJ9q0ULCZUyzaX4nbTEk3CifWJ1/htU5sECmUxh6V3ib4yqT3w
 o+UULZ5qW1B6zhkkLN18j8YoUuriQKPZmtVw4VS67icb0arVniGiFWGlsk8rbMfa
 1gO3TnlAqjKdKUxTy72XruMQQLzUTlq+RpZgWeH0wEaHM8np5b+QdFLkQGsf+r0U
 YL7yqavfPYbwSauhs/EYZXCSokD1u1ocGRfvzVcqeB0SFhp227qzcK9yY2nq3PXg
 B3kZddBUewI8LGQey3US52cFrxCB9PZuU8kcz1WGpnGIHGqrBjLZkM51jwW3L2bU
 jsgj1RMszNv1JKk0tfVJuwKdv0cHjfkH94ew8RtbndG6PIbS0300Pm0/SwBPavcc
 ZYPbB+oS6NYWmxw7v+HVQwZYKSwex3OLHPlv/GzjrF+jAObJCVU=
 =nAfm
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWEb24ACgkQYKtH/8kJ
 UifdNxAAuy/+rubxbHpGktGKETLIKHFSrd0ExGgwhsFEcx5/k61Lyb6xfVlUF4sA
 U3gslHrnbrRT/ijA8h5T/teZFIUk4FVI0mZhgLwDhtpaTxJtP6nHYKGk4AOe6oTI
 MKL55sv5bpKY5G0JVtrmC36wbBoQTJUvQJ8oKpTSdvSngude6Ab1g52O3mZV8rjc
 IFSmJRMdr/f6OoCh+SmjV3lKc3KGBxO23sxgN259wgnpJePWhZNDFLzgyDLRa2xG
 EK2DsazYhsmOT9IFy0znHfSBNtefBkahBgDiPkXw0JWg9ElhInBKpmZQ/R6QNxBH
 gV+WPxzu4EJZVygkxMnRTPHpreP7KDHRZshYPpRluFfuSMcZQpejb+8M6uOHTc4u
 34BSGaaLeCj35/Ews3ii99OZwJ4hYyl4yYgZDwUlcyZqRWfO2JC6vQzssqacLwVm
 wqm4by3OWWOmtbrf7+IGZZUv8bicULntoXdnVKo4PjQMWNFHAEnV8Ad/xh5M+U0q
 6uxyRlujp99D5i7Q6Pc+/NL20UAAnJ9oTz4Tnmpp4jzxexxERKj9g2OTbuXHKgWW
 nZSickM7dA2B37HiplyF3o4in5ko+GffAY1BK+6cKoIFXezPfkn4044D+EV6TL/I
 FffjMHJDuurop2gSACEfakfWyM8qWp0paJe2f+9746zy57LpJx0=
 =eoXg
 -----END PGP SIGNATURE-----

Merge tag 'ti-k3-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt

TI K3 device tree updates for v6.8

New features across K3 SoCs:
- ov5640 and imx219 sensor overlays added to various am62x/am62a boards.
- TP6594 and family support for J7200, j721s2,j721e, am69/j784s4 boards

Generic Fixes:
- minor white space cleanups
- Addition of optional regs for more complete DMA description across all K3
  SoCs.

Misc:
- chip_id node moves under wkup_conf bus.
- COMPILE_TEST+OF_ALL_DTBS is now standard usage for testing overlays.

SoC specific Fixes/Features:
AM62A
 - gpio pin count fixups.
AM625
 - Adds verdin am62x-mallow board
 - Adds IMG's AXE-RGX GPU support
 - Adds gpio-ranges support for main domain GPIOs.
 - SK now defaults to mcu gpio marked as reserved to cater to MCU use cases
AM64
 - EVM/SK now defaults to mcu gpio marked as reserved to cater to MCU use cases
AM65
 - Fix for DSS Irq trigger type, proper fixup for dss-oldi-io-ctrl node
 - misc splitup to make AM652 device variant reusable
J7200
 - mmc: itap delay fixups for DDR52
J721S2/AM68
 - mmc: itap delay fixups for DDR50
J784S4/AM69
 - mmc: itap delay fixups for DDR50

Board specific fixes/Features:
- iot2050 cleanups for enabling icssg-prueth nodes, runtime pinmuxing,
  dropping ecap0pwm nodes, misc cleanups.
- am62x-verdin adds uart2, minor fixups for spi1 chip-select pinctrl
- am62-phycore adds hdmi support
- am64-phycore adds R5F support.
- am62x-beagleplay renames console uart pinmuxes.

* tag 'ti-k3-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (56 commits)
  arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode
  arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
  arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode
  arm64: dts: ti: k3-am6*: Add additional regs for DMA components
  arm64: dts: ti: k3-j7*: Add additional regs for DMA components
  arm64: dts: ti: k3-am65: Add additional regs for DMA components
  arm64: dts: ti: k3-am62-main: Add GPU device node
  arm64: dts: ti: k3-j721s2-evm: Add overlay for PCIE1 Endpoint Mode
  arm64: dts: ti: k3-j721e-evm: Add overlay for PCIE0 Endpoint Mode
  arm64: dts: ti: k3-j721e-sk: Add TPS6594 family PMICs
  arm64: dts: ti: k3-am69-sk: Add support for TPS6594 PMIC
  arm64: dts: ti: k3-j784s4-evm: Add support for TPS6594 PMIC
  arm64: dts: ti: k3-j721e-som-p0: Add TP6594 family PMICs
  arm64: dts: ti: k3-j721s2-som-p0: Add TP6594 family PMICs
  arm64: dts: ti: k3-j7200-som-p0: Add TP6594 family PMICs
  arm64: dts: ti: Add verdin am62 mallow board
  dt-bindings: arm: ti: Add verdin am62 mallow board
  arm64: dts: ti: verdin-am62: Improve spi1 chip-select pinctrl
  arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Remove HDMI Reset Line Name
  arm64: dts: ti: k3-am625-phyboard-lyra-rdk: Add HDMI support
  ...

Link: https://lore.kernel.org/r/20231218153115.szyd22tmoumqkn6g@occupier
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-12-21 17:01:15 +00:00
commit 7af9a9f5e9
57 changed files with 3183 additions and 165 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/ti/k3.yaml
View File

@ -50,6 +50,7 @@ properties:
- enum:
- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
- toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
- const: toradex,verdin-am62 # Verdin AM62 Module
@ -60,6 +61,7 @@ properties:
- enum:
- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
- toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
- const: toradex,verdin-am62 # Verdin AM62 Module

70
arch/arm64/boot/dts/ti/Makefile
View File

@ -9,20 +9,20 @@
# alphabetically.
# Boards with AM62x SoC
k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo
k3-am62-lp-sk-hdmi-audio-dtbs := k3-am62-lp-sk.dtb k3-am62x-sk-hdmi-audio.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-ov5640.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-hdmi-audio.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-hdmi-audio.dtb
# Boards with AM62Ax SoC
dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
@ -30,19 +30,19 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
# Boards with AM62Px SoC
dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
# Common overlays for SK-AM62* family of boards
dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-ov5640.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-tevi-ov5640.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-imx219.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo
# Boards with AM64x SoC
dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb
k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \
k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \
k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
# Boards with AM65x SoC
k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo
@ -67,6 +67,7 @@ k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-e
dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
# Boards with J721s2 SoC
@ -75,14 +76,59 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
k3-j721s2-evm-dtbs := k3-j721s2-common-proc-board.dtb k3-j721s2-evm-gesi-exp-board.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
# Build time test only, enabled by CONFIG_OF_ALL_DTBS
k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \
k3-am625-beagleplay-csi2-ov5640.dtbo
k3-am625-beagleplay-csi2-tevi-ov5640-dtbs := k3-am625-beagleplay.dtb \
k3-am625-beagleplay-csi2-tevi-ov5640.dtbo
k3-am625-sk-csi2-imx219-dtbs := k3-am625-sk.dtb \
k3-am62x-sk-csi2-imx219.dtbo
k3-am625-sk-csi2-ov5640-dtbs := k3-am625-sk.dtb \
k3-am62x-sk-csi2-ov5640.dtbo
k3-am625-sk-csi2-tevi-ov5640-dtbs := k3-am625-sk.dtb \
k3-am62x-sk-csi2-tevi-ov5640.dtbo
k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo
k3-am62-lp-sk-hdmi-audio-dtbs := k3-am62-lp-sk.dtb k3-am62x-sk-hdmi-audio.dtbo
k3-am62a7-sk-csi2-imx219-dtbs := k3-am62a7-sk.dtb \
k3-am62x-sk-csi2-imx219.dtbo
k3-am62a7-sk-csi2-ov5640-dtbs := k3-am62a7-sk.dtb \
k3-am62x-sk-csi2-ov5640.dtbo
k3-am62a7-sk-csi2-tevi-ov5640-dtbs := k3-am62a7-sk.dtb \
k3-am62x-sk-csi2-tevi-ov5640.dtbo
k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \
k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo
k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \
k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo
k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \
k3-j721e-evm-pcie0-ep.dtbo
k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \
k3-j721s2-evm-pcie1-ep.dtbo
dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am625-beagleplay-csi2-tevi-ov5640.dtb \
k3-am625-sk-csi2-imx219.dtb \
k3-am625-sk-csi2-ov5640.dtb \
k3-am625-sk-csi2-tevi-ov5640.dtb \
k3-am625-sk-hdmi-audio.dtb \
k3-am62-lp-sk-hdmi-audio.dtb \
k3-am62a7-sk-csi2-imx219.dtb \
k3-am62a7-sk-csi2-ov5640.dtb \
k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \
k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \
k3-j721e-evm-pcie0-ep.dtb \
k3-j721s2-evm-pcie1-ep.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am625-beagleplay += -@
DTC_FLAGS_k3-am625-sk += -@
DTC_FLAGS_k3-am62-lp-sk += -@
DTC_FLAGS_k3-am62a7-sk += -@
DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@
DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
DTC_FLAGS_k3-j721e-common-proc-board += -@
DTC_FLAGS_k3-j721s2-common-proc-board += -@

96
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
View File

@ -121,8 +121,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>,
<0x00 0x48420000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
@ -138,8 +143,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x1000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
@ -502,6 +512,9 @@
main_gpio0: gpio@600000 {
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00600000 0x0 0x100>;
gpio-ranges = <&main_pmx0 0 0 32>,
<&main_pmx0 32 33 38>,
<&main_pmx0 70 72 22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
@ -520,6 +533,10 @@
compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x00601000 0x0 0x100>;
gpio-controller;
gpio-ranges = <&main_pmx0 0 94 41>,
<&main_pmx0 41 136 6>,
<&main_pmx0 47 143 3>,
<&main_pmx0 50 149 2>;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio_intr>;
interrupts = <180>, <181>, <182>,
@ -675,6 +692,15 @@
};
};
gpu: gpu@fd00000 {
compatible = "ti,am62-gpu", "img,img-axe";
reg = <0x00 0x0fd00000 0x00 0x20000>;
clocks = <&k3_clks 187 0>;
clock-names = "core";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
};
cpsw3g: ethernet@8000000 {
compatible = "ti,am642-cpsw-nuss";
#address-cells = <2>;
@ -965,4 +991,66 @@
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
ti_csi2rx0: ticsi2rx@30102000 {
compatible = "ti,j721e-csi2rx-shim";
dmas = <&main_bcdma 0 0x4700 0>;
dma-names = "rx0";
reg = <0x00 0x30102000 0x00 0x1000>;
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
cdns_csi2rx0: csi-bridge@30101000 {
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
reg = <0x00 0x30101000 0x00 0x1000>;
clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
<&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy0>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi0_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi0_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi0_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi0_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
dphy0: phy@30110000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x30110000 0x00 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
};

3
arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi
View File

@ -214,6 +214,5 @@
/* Verdin UART_2 */
&wkup_uart0 {
/* FIXME: WKUP UART0 is used by DM firmware */
status = "reserved";
status = "okay";
};

3
arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi
View File

@ -235,6 +235,5 @@
/* Verdin UART_2 */
&wkup_uart0 {
/* FIXME: WKUP UART0 is used by DM firmware */
status = "reserved";
status = "okay";
};

188
arch/arm64/boot/dts/ti/k3-am62-verdin-mallow.dtsi Normal file
View File

@ -0,0 +1,188 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* Common dtsi for Verdin AM62 SoM on Mallow carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/mallow-carrier-board
*/
#include <dt-bindings/leds/common.h>
/ {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_clk_gpio>,
<&pinctrl_qspi1_cs_gpio>,
<&pinctrl_qspi1_io0_gpio>,
<&pinctrl_qspi1_io1_gpio>;
/* SODIMM 52 - USER_LED_1_RED */
led-0 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 54 - USER_LED_1_GREEN */
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <1>;
gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 56 - USER_LED_2_RED */
led-2 {
color = <LED_COLOR_ID_RED>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
};
/* SODIMM 58 - USER_LED_2_GREEN */
led-3 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_DEBUG;
function-enumerator = <2>;
gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
};
};
};
/* Verdin ETH */
&cpsw3g {
status = "okay";
};
/* Verdin MDIO */
&cpsw3g_mdio {
status = "okay";
};
/* Verdin ETH_1*/
&cpsw_port1 {
status = "okay";
};
/* Verdin PWM_1 and PWM_2*/
&epwm0 {
status = "okay";
};
/* Verdin PWM_3 DSI */
&epwm1 {
status = "okay";
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>,
<&pinctrl_gpio_1>,
<&pinctrl_gpio_2>,
<&pinctrl_gpio_3>,
<&pinctrl_gpio_4>;
};
/* Verdin I2C_1 */
&main_i2c1 {
status = "okay";
/* Temperature sensor */
sensor@4f {
compatible = "ti,tmp1075";
reg = <0x4f>;
};
/* EEPROM */
eeprom@57 {
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
};
/* Verdin I2C_2 DSI */
&main_i2c2 {
status = "okay";
};
/* Verdin I2C_4 CSI */
&main_i2c3 {
status = "okay";
};
/* Verdin CAN_1 */
&main_mcan0 {
status = "okay";
};
/* Verdin SPI_1 */
&main_spi1 {
pinctrl-0 = <&pinctrl_spi1>,
<&pinctrl_spi1_cs0>,
<&pinctrl_qspi1_cs2_gpio>;
cs-gpios = <0>, <&main_gpio0 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* Verdin UART_3 */
&main_uart0 {
status = "okay";
};
/* Verdin UART_1 */
&main_uart1 {
status = "okay";
};
/* Verdin I2C_3_HDMI */
&mcu_i2c0 {
status = "okay";
};
/* Verdin CAN_2 */
&mcu_mcan0 {
status = "okay";
};
/* Verdin UART_4 */
&mcu_uart0 {
status = "okay";
};
/* Verdin SD_1 */
&sdhci1 {
status = "okay";
};
/* Verdin USB_1 */
&usbss0 {
status = "okay";
};
&usb0 {
status = "okay";
};
/* Verdin USB_2 */
&usbss1 {
status = "okay";
};
&usb1 {
status = "okay";
};
/* Verdin CTRL_WAKE1_MICO# */
&verdin_gpio_keys {
status = "okay";
};
/* Verdin UART_2 */
&wkup_uart0 {
status = "okay";
};

3
arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi
View File

@ -207,6 +207,5 @@
/* Verdin UART_2 */
&wkup_uart0 {
/* FIXME: WKUP UART0 is used by DM firmware */
status = "reserved";
status = "okay";
};

17
arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
View File

@ -233,6 +233,13 @@
>;
};
/* Verdin SPI_1 CS as GPIO */
pinctrl_qspi1_io4_gpio: main-gpio0-7-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x001c, PIN_INPUT, 7) /* (J23) OSPI0_D4.GPIO0_7 */ /* SODIMM 202 */
>;
};
/* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */
pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins {
pinctrl-single,pins = <
@ -599,12 +606,18 @@
pinctrl_spi1: main-spi1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */
AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */
AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */
AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */
>;
};
/* Verdin SPI_1 CS */
pinctrl_spi1_cs0: main-spi1-cs0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */
>;
};
/* ETH_25MHz_CLK */
pinctrl_eth_clock: main-system-clkout0-default-pins {
pinctrl-single,pins = <
@ -1278,7 +1291,7 @@
/* Verdin SPI_1 */
&main_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
pinctrl-0 = <&pinctrl_spi1>, <&pinctrl_spi1_cs0>;
ti,pindir-d0-out-d1-in;
status = "disabled";
};

77
arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-ov5640.dtso Normal file
View File

@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0
/*
* ALINX AN5641 & Digilent PCam 5C - OV5640 camera module
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
clk_ov5640_fixed: ov5640-xclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
};
&main_gpio0 {
p11-hog {
/* P11 - CSI2_CAMERA_GPIO1 */
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "CSI2_CAMERA_GPIO1";
};
};
&wkup_i2c0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2rx0_in_sensor>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&cdns_csi2rx0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "okay";
csi2rx0_in_sensor: endpoint {
remote-endpoint = <&csi2_cam0>;
bus-type = <4>; /* CSI2 DPHY. */
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&dphy0 {
status = "okay";
};
&ti_csi2rx0 {
status = "okay";
};

77
arch/arm64/boot/dts/ti/k3-am625-beagleplay-csi2-tevi-ov5640.dtso Normal file
View File

@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Technexion TEVI-OV5640-*-RPI - OV5640 camera module
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
clk_ov5640_fixed: ov5640-xclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&main_gpio0 {
p11-hog {
/* P11 - CSI2_CAMERA_GPIO1 */
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "CSI2_CAMERA_GPIO1";
};
};
&wkup_i2c0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2rx0_in_sensor>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&cdns_csi2rx0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "okay";
csi2rx0_in_sensor: endpoint {
remote-endpoint = <&csi2_cam0>;
bus-type = <4>; /* CSI2 DPHY. */
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&dphy0 {
status = "okay";
};
&ti_csi2rx0 {
status = "okay";
};

4
arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
View File

@ -443,7 +443,7 @@
>;
};
console_pins_default: console-default-pins {
main_uart0_pins_default: main-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
@ -877,7 +877,7 @@
&main_uart0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&console_pins_default>;
pinctrl-0 = <&main_uart0_pins_default>;
status = "okay";
};

98
arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts
View File

@ -35,6 +35,18 @@
standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>;
};
hdmi0: connector-hdmi {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&sii9022_out>;
};
};
};
keys {
compatible = "gpio-keys";
autorepeat;
@ -93,6 +105,37 @@
>;
};
hdmi_int_pins_default: hdmi-int-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */
>;
};
main_dss0_pins_default: main-dss0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */
AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */
AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */
AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */
AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */
AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */
AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */
AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */
AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */
AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */
AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */
AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */
AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */
AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */
AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */
AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */
AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */
AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */
AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */
AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */
>;
};
main_i2c1_pins_default: main-i2c1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
@ -184,10 +227,30 @@
};
};
&dss {
pinctrl-names = "default";
pinctrl-0 = <&main_dss0_pins_default>;
status = "okay";
};
&dss_ports {
#address-cells = <1>;
#size-cells = <0>;
/* VP2: DPI/HDMI Output */
port@1 {
reg = <1>;
dpi1_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};
};
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
clock-frequency = <100000>;
status = "okay";
gpio_exp: gpio-expander@21 {
@ -201,12 +264,43 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
gpio-line-names = "GPIO0_HDMI_RST", "GPIO1_CAN0_nEN",
gpio-line-names = "", "GPIO1_CAN0_nEN",
"GPIO2_LED2", "GPIO3_LVDS_GPIO",
"GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN",
"GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET";
};
sii9022: bridge-hdmi@39 {
compatible = "sil,sii9022";
reg = <0x39>;
interrupt-parent = <&main_gpio0>;
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_int_pins_default>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sii9022_in: endpoint {
remote-endpoint = <&dpi1_out>;
};
};
port@1 {
reg = <1>;
sii9022_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
eeprom@51 {
compatible = "atmel,24c02";
pagesize = <16>;

22
arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-mallow.dts Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/mallow-carrier-board
*/
/dts-v1/;
#include "k3-am625.dtsi"
#include "k3-am62-verdin.dtsi"
#include "k3-am62-verdin-nonwifi.dtsi"
#include "k3-am62-verdin-mallow.dtsi"
/ {
model = "Toradex Verdin AM62 on Mallow Board";
compatible = "toradex,verdin-am62-nonwifi-mallow",
"toradex,verdin-am62-nonwifi",
"toradex,verdin-am62",
"ti,am625";
};

22
arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-mallow.dts Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2023 Toradex
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
* https://www.toradex.com/products/carrier-board/mallow-carrier-board
*/
/dts-v1/;
#include "k3-am625.dtsi"
#include "k3-am62-verdin.dtsi"
#include "k3-am62-verdin-wifi.dtsi"
#include "k3-am62-verdin-mallow.dtsi"
/ {
model = "Toradex Verdin AM62 WB on Mallow Board";
compatible = "toradex,verdin-am62-wifi-mallow",
"toradex,verdin-am62-wifi",
"toradex,verdin-am62",
"ti,am625";
};

121
arch/arm64/boot/dts/ti/k3-am62a-main.dtsi
View File

@ -101,8 +101,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>,
<0x00 0x48420000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
@ -117,8 +122,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x1000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
ti,sci = <&dmsc>;
@ -144,6 +154,44 @@
};
};
dmss_csi: bus@4e000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-ranges;
ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>;
ti,sci-dev-id = <198>;
inta_main_dmss_csi: interrupt-controller@4e0a0000 {
compatible = "ti,sci-inta";
reg = <0x00 0x4e0a0000 0x00 0x8000>;
#interrupt-cells = <0>;
interrupt-controller;
interrupt-parent = <&gic500>;
msi-controller;
ti,sci = <&dmsc>;
ti,sci-dev-id = <200>;
ti,interrupt-ranges = <0 237 8>;
ti,unmapped-event-sources = <&main_bcdma_csi>;
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
};
main_bcdma_csi: dma-controller@4e230000 {
compatible = "ti,am62a-dmss-bcdma-csirx";
reg = <0x00 0x4e230000 0x00 0x100>,
<0x00 0x4e180000 0x00 0x8000>,
<0x00 0x4e100000 0x00 0x10000>;
reg-names = "gcfg", "rchanrt", "ringrt";
msi-parent = <&inta_main_dmss_csi>;
#dma-cells = <3>;
ti,sci = <&dmsc>;
ti,sci-dev-id = <199>;
ti,sci-rm-range-rchan = <0x21>;
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
};
};
dmsc: system-controller@44043000 {
compatible = "ti,k2g-sci";
reg = <0x00 0x44043000 0x00 0xfe0>;
@ -462,7 +510,7 @@
<193>, <194>, <195>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <87>;
ti,ngpio = <92>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 77 0>;
@ -480,7 +528,7 @@
<183>, <184>, <185>;
interrupt-controller;
#interrupt-cells = <2>;
ti,ngpio = <88>;
ti,ngpio = <52>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 78 0>;
@ -876,4 +924,65 @@
power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
ti_csi2rx0: ticsi2rx@30102000 {
compatible = "ti,j721e-csi2rx-shim";
dmas = <&main_bcdma_csi 0 0x5000 0>;
dma-names = "rx0";
reg = <0x00 0x30102000 0x00 0x1000>;
power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
cdns_csi2rx0: csi-bridge@30101000 {
compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
reg = <0x00 0x30101000 0x00 0x1000>;
clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>,
<&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>;
clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
phys = <&dphy0>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "disabled";
};
csi0_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi0_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi0_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi0_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
};
dphy0: phy@30110000 {
compatible = "cdns,dphy-rx";
reg = <0x00 0x30110000 0x00 0x1100>;
#phy-cells = <0>;
power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
status = "disabled";
};
};

39
arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
View File

@ -274,6 +274,12 @@
AM62AX_IOPAD(0x084, PIN_INPUT, 2) /* (L18) GPMC0_ADVn_ALE.MCASP1_AXR2 */
>;
};
main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins {
pinctrl-single,pins = <
AM62AX_IOPAD(0x01d4, PIN_INPUT, 7) /* (C15) UART0_RTSn.GPIO1_23 */
>;
};
};
&mcu_pmx0 {
@ -407,6 +413,12 @@
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&main_gpio1>;
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
"BT_EN_SOC", "MMC1_SD_EN",
@ -434,6 +446,33 @@
DRVDD-supply = <&vcc_3v3_sys>;
DVDD-supply = <&buck5>;
};
exp2: gpio@23 {
compatible = "ti,tca6424";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "", "",
"", "",
"", "",
"", "",
"WL_LT_EN", "CSI_RSTz",
"", "",
"", "",
"", "",
"SPI0_FET_SEL", "SPI0_FET_OE",
"RGMII2_BRD_CONN_DET", "CSI_SEL2",
"CSI_EN", "AUTO_100M_1000M_CONFIG",
"CSI_VLDO_SEL", "SoC_WLAN_SDIO_RST";
};
};
&main_i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&sdhci1 {

18
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
View File

@ -101,8 +101,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>,
<0x00 0x48420000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
@ -119,8 +124,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x10000>,
<0x00 0x484a0000 0x00 0x2000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x1000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
bootph-all;

9
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
View File

@ -598,3 +598,12 @@
status = "reserved";
bootph-all;
};
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_gpio_intr {
status = "reserved";
};

16
arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
View File

@ -399,6 +399,13 @@
};
};
&main_i2c2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&sdhci0 {
bootph-all;
status = "okay";
@ -517,3 +524,12 @@
};
};
};
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_gpio_intr {
status = "reserved";
};

84
arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-imx219.dtso Normal file
View File

@ -0,0 +1,84 @@
// SPDX-License-Identifier: GPL-2.0
/*
* IMX219 (RPi v2) Camera Module
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
clk_imx219_fixed: imx219-xclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&main_i2c2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9543";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
/* CAM port */
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
ov5640: camera@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&clk_imx219_fixed>;
clock-names = "xclk";
reset-gpios = <&exp1 13 GPIO_ACTIVE_HIGH>;
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2rx0_in_sensor>;
link-frequencies = /bits/ 64 <456000000>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
};
};
&cdns_csi2rx0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "okay";
csi2rx0_in_sensor: endpoint {
remote-endpoint = <&csi2_cam0>;
bus-type = <4>; /* CSI2 DPHY. */
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&ti_csi2rx0 {
status = "okay";
};
&dphy0 {
status = "okay";
};

82
arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-ov5640.dtso Normal file
View File

@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0
/*
* ALINX AN5641 & Digilent PCam 5C - OV5640 camera module
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
clk_ov5640_fixed: ov5640-xclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
};
&main_i2c2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9543";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
/* CAM port */
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>;
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2rx0_in_sensor>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
};
};
&cdns_csi2rx0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "okay";
csi2rx0_in_sensor: endpoint {
remote-endpoint = <&csi2_cam0>;
bus-type = <4>; /* CSI2 DPHY. */
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&ti_csi2rx0 {
status = "okay";
};
&dphy0 {
status = "okay";
};

82
arch/arm64/boot/dts/ti/k3-am62x-sk-csi2-tevi-ov5640.dtso Normal file
View File

@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Technexion TEVI-OV5640-*-RPI - OV5640 camera module
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
clk_ov5640_fixed: ov5640-xclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&main_i2c2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
i2c-switch@71 {
compatible = "nxp,pca9543";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x71>;
/* CAM port */
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
ov5640: camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
powerdown-gpios = <&exp1 13 GPIO_ACTIVE_LOW>;
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2rx0_in_sensor>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
};
};
&cdns_csi2rx0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "okay";
csi2rx0_in_sensor: endpoint {
remote-endpoint = <&csi2_cam0>;
bus-type = <4>; /* CSI2 DPHY. */
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&ti_csi2rx0 {
status = "okay";
};
&dphy0 {
status = "okay";
};

22
arch/arm64/boot/dts/ti/k3-am64-main.dtsi
View File

@ -63,7 +63,7 @@
#phy-cells = <1>;
};
epwm_tbclk: clock-controller@4140 {
epwm_tbclk: clock-controller@4130 {
compatible = "ti,am64-epwm-tbclk";
reg = <0x4130 0x4>;
#clock-cells = <1>;
@ -138,8 +138,13 @@
<0x00 0x4c000000 0x00 0x20000>,
<0x00 0x4a820000 0x00 0x20000>,
<0x00 0x4aa40000 0x00 0x20000>,
<0x00 0x4bc00000 0x00 0x100000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4bc00000 0x00 0x100000>,
<0x00 0x48600000 0x00 0x8000>,
<0x00 0x484a4000 0x00 0x2000>,
<0x00 0x484c2000 0x00 0x2000>,
<0x00 0x48420000 0x00 0x2000>;
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "bchan";
msi-parent = <&inta_main_dmss>;
#dma-cells = <3>;
@ -155,8 +160,13 @@
reg = <0x00 0x485c0000 0x00 0x100>,
<0x00 0x4a800000 0x00 0x20000>,
<0x00 0x4aa00000 0x00 0x40000>,
<0x00 0x4b800000 0x00 0x400000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
<0x00 0x4b800000 0x00 0x400000>,
<0x00 0x485e0000 0x00 0x20000>,
<0x00 0x484a0000 0x00 0x4000>,
<0x00 0x484c0000 0x00 0x2000>,
<0x00 0x48430000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
"ring", "tchan", "rchan", "rflow";
msi-parent = <&inta_main_dmss>;
#dma-cells = <2>;
@ -623,6 +633,7 @@
ti,otap-del-sel-mmc-hs = <0x0>;
ti,otap-del-sel-ddr52 = <0x6>;
ti,otap-del-sel-hs200 = <0x7>;
status = "disabled";
};
sdhci1: mmc@fa00000 {
@ -641,6 +652,7 @@
ti,otap-del-sel-sdr104 = <0x6>;
ti,otap-del-sel-ddr50 = <0x9>;
ti,clkbuf-sel = <0x7>;
status = "disabled";
};
cpsw3g: ethernet@8000000 {

103
arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
View File

@ -29,7 +29,7 @@
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -39,6 +39,54 @@
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
};
leds {
@ -166,6 +214,34 @@
status = "disabled";
};
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&main_i2c0 {
status = "okay";
pinctrl-names = "default";
@ -191,6 +267,30 @@
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&ospi0 {
status = "okay";
pinctrl-names = "default";
@ -211,6 +311,7 @@
};
&sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;

12
arch/arm64/boot/dts/ti/k3-am642-evm.dts
View File

@ -468,11 +468,15 @@
bootph-all;
};
/* mcu_gpio0 is reserved for mcu firmware usage */
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_gpio_intr {
status = "reserved";
};
&main_spi0 {
status = "okay";
pinctrl-names = "default";
@ -487,17 +491,19 @@
};
};
/* eMMC */
&sdhci0 {
/* emmc */
status = "okay";
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
/* SD/MMC */
&sdhci1 {
/* SD/MMC */
bootph-all;
status = "okay";
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;

1
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
View File

@ -264,6 +264,7 @@
};
&sdhci1 {
status = "okay";
vmmc-supply = <&vcc_3v3_mmc>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;

10
arch/arm64/boot/dts/ti/k3-am642-sk.dts
View File

@ -433,12 +433,17 @@
};
};
/* mcu_gpio0 is reserved for mcu firmware usage */
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_gpio_intr {
status = "reserved";
};
&sdhci0 {
status = "okay";
vmmc-supply = <&wlan_en>;
bus-width = <4>;
non-removable;
@ -458,9 +463,10 @@
};
};
/* SD/MMC */
&sdhci1 {
/* SD/MMC */
bootph-all;
status = "okay";
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;

1
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
View File

@ -425,7 +425,6 @@
ti,driver-strength-ohm = <50>;
ti,fails-without-test-cd;
/* Enabled by overlay */
status = "disabled";
};
&tscadc0 {

1
arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi
View File

@ -219,6 +219,7 @@
};
&sdhci0 {
status = "okay";
non-removable;
disable-wp;
no-sdio;

10
arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) Siemens AG, 2021
* Copyright (c) Siemens AG, 2021-2023
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
@ -44,3 +44,11 @@
&tx_pru2_1 {
status = "disabled";
};
&icssg0_eth {
status = "disabled";
};
&icssg0_mdio {
status = "disabled";
};

4
arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi
View File

@ -20,7 +20,9 @@
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&cp2102n_reset_pin_default>;
pinctrl-0 =
<&main_pcie_enable_pins_default>,
<&cp2102n_reset_pin_default>;
gpio-line-names =
"", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",

826
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
View File

@ -9,14 +9,26 @@
* Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2
*/
#include "k3-am654.dtsi"
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
aliases {
serial0 = &wkup_uart0;
serial1 = &mcu_uart0;
serial2 = &main_uart0;
serial3 = &main_uart1;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &main_i2c0;
i2c3 = &main_i2c1;
i2c4 = &main_i2c2;
i2c5 = &main_i2c3;
spi0 = &mcu_spi0;
mmc0 = &sdhci1;
mmc1 = &sdhci0;
ethernet1 = &icssg0_emac0;
ethernet2 = &icssg0_emac1;
};
chosen {
@ -101,9 +113,498 @@
#clock-cells = <0>;
clock-frequency = <19200000>;
};
/* Dual Ethernet application node on PRU-ICSSG0 */
icssg0_eth: icssg0-eth {
compatible = "ti,am654-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&icssg0_rgmii_pins_default>;
sram = <&msmc_ram>;
ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>,
<&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
ti,mii-g-rt = <&icssg0_mii_g_rt>;
ti,mii-rt = <&icssg0_mii_rt>;
ti,iep = <&icssg0_iep0>, <&icssg0_iep1>;
interrupt-parent = <&icssg0_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_udmap 0xc100>, /* egress slice 0 */
<&main_udmap 0xc101>, /* egress slice 0 */
<&main_udmap 0xc102>, /* egress slice 0 */
<&main_udmap 0xc103>, /* egress slice 0 */
<&main_udmap 0xc104>, /* egress slice 1 */
<&main_udmap 0xc105>, /* egress slice 1 */
<&main_udmap 0xc106>, /* egress slice 1 */
<&main_udmap 0xc107>, /* egress slice 1 */
<&main_udmap 0x4100>, /* ingress slice 0 */
<&main_udmap 0x4101>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
icssg0_emac0: port@0 {
reg = <0>;
phy-handle = <&icssg0_eth0_phy>;
phy-mode = "rgmii-id";
ti,syscon-rgmii-delay = <&scm_conf 0x4100>;
ti,half-duplex-capable;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
icssg0_emac1: port@1 {
reg = <1>;
phy-handle = <&icssg0_eth1_phy>;
phy-mode = "rgmii-id";
ti,syscon-rgmii-delay = <&scm_conf 0x4104>;
ti,half-duplex-capable;
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};
};
&wkup_pmx0 {
pinctrl-names =
"default",
"d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
"d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
"d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
"d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
"d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
"d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
"d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
"d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown",
"a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown",
"a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown",
"a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown",
"a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown",
"a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown",
"a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown";
pinctrl-0 = <&d0_uart0_rxd>;
pinctrl-1 = <&d0_uart0_rxd>;
pinctrl-2 = <&d0_gpio>;
pinctrl-3 = <&d0_gpio_pullup>;
pinctrl-4 = <&d0_gpio_pulldown>;
pinctrl-5 = <&d1_uart0_txd>;
pinctrl-6 = <&d1_gpio>;
pinctrl-7 = <&d1_gpio_pullup>;
pinctrl-8 = <&d1_gpio_pulldown>;
pinctrl-9 = <&d2_uart0_ctsn>;
pinctrl-10 = <&d2_gpio>;
pinctrl-11 = <&d2_gpio_pullup>;
pinctrl-12 = <&d2_gpio_pulldown>;
pinctrl-13 = <&d3_uart0_rtsn>;
pinctrl-14 = <&d3_gpio>;
pinctrl-15 = <&d3_gpio_pullup>;
pinctrl-16 = <&d3_gpio_pulldown>;
pinctrl-17 = <&d10_spi0_cs0>;
pinctrl-18 = <&d10_gpio>;
pinctrl-19 = <&d10_gpio_pullup>;
pinctrl-20 = <&d10_gpio_pulldown>;
pinctrl-21 = <&d11_spi0_d0>;
pinctrl-22 = <&d11_gpio>;
pinctrl-23 = <&d11_gpio_pullup>;
pinctrl-24 = <&d11_gpio_pulldown>;
pinctrl-25 = <&d12_spi0_d1>;
pinctrl-26 = <&d12_gpio>;
pinctrl-27 = <&d12_gpio_pullup>;
pinctrl-28 = <&d12_gpio_pulldown>;
pinctrl-29 = <&d13_spi0_clk>;
pinctrl-30 = <&d13_gpio>;
pinctrl-31 = <&d13_gpio_pullup>;
pinctrl-32 = <&d13_gpio_pulldown>;
pinctrl-33 = <&a0_gpio>;
pinctrl-34 = <&a0_gpio_pullup>;
pinctrl-35 = <&a0_gpio_pulldown>;
pinctrl-36 = <&a1_gpio>;
pinctrl-37 = <&a1_gpio_pullup>;
pinctrl-38 = <&a1_gpio_pulldown>;
pinctrl-39 = <&a2_gpio>;
pinctrl-40 = <&a2_gpio_pullup>;
pinctrl-41 = <&a2_gpio_pulldown>;
pinctrl-42 = <&a3_gpio>;
pinctrl-43 = <&a3_gpio_pullup>;
pinctrl-44 = <&a3_gpio_pulldown>;
pinctrl-45 = <&a4_gpio>;
pinctrl-46 = <&a4_gpio_pullup>;
pinctrl-47 = <&a4_gpio_pulldown>;
pinctrl-48 = <&a5_gpio>;
pinctrl-49 = <&a5_gpio_pullup>;
pinctrl-50 = <&a5_gpio_pulldown>;
d0_uart0_rxd: d0-uart0-rxd-pins {
pinctrl-single,pins = <
/* (P4) MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
>;
};
d0_gpio: d0-gpio-pins {
pinctrl-single,pins = <
/* (P4) WKUP_GPIO0_29 */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7)
>;
};
d0_gpio_pullup: d0-gpio-pullup-pins {
pinctrl-single,pins = <
/* (P4) WKUP_GPIO0_29 */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7)
>;
};
d0_gpio_pulldown: d0-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (P4) WKUP_GPIO0_29 */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7)
>;
};
d1_uart0_txd: d1-uart0-txd-pins {
pinctrl-single,pins = <
/* (P5) MCU_UART0_TXD */
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
>;
};
d1_gpio: d1-gpio-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_30 */
AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
>;
};
d1_gpio_pullup: d1-gpio-pullup-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_30 */
AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7)
>;
};
d1_gpio_pulldown: d1-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_30 */
AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7)
>;
};
d2_uart0_ctsn: d2-uart0-ctsn-pins {
pinctrl-single,pins = <
/* (P1) MCU_UART0_CTSn */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4)
>;
};
d2_gpio: d2-gpio-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
>;
};
d2_gpio_pullup: d2-gpio-pullup-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7)
>;
};
d2_gpio_pulldown: d2-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (P5) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7)
>;
};
d3_uart0_rtsn: d3-uart0-rtsn-pins {
pinctrl-single,pins = <
/* (N3) MCU_UART0_RTSn */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4)
>;
};
d3_gpio: d3-gpio-pins {
pinctrl-single,pins = <
/* (N3) WKUP_GPIO0_33 */
AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7)
>;
};
d3_gpio_pullup: d3-gpio-pullup-pins {
pinctrl-single,pins = <
/* (N3) WKUP_GPIO0_33 */
AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7)
>;
};
d3_gpio_pulldown: d3-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (N3) WKUP_GPIO0_33 */
AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7)
>;
};
d10_spi0_cs0: d10-spi0-cs0-pins {
pinctrl-single,pins = <
/* (Y4) MCU_SPI0_CS0 */
AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
>;
};
d10_gpio: d10-gpio-pins {
pinctrl-single,pins = <
/* (Y4) WKUP_GPIO0_51 */
AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7)
>;
};
d10_gpio_pullup: d10-gpio-pullup-pins {
pinctrl-single,pins = <
/* (Y4) WKUP_GPIO0_51 */
AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7)
>;
};
d10_gpio_pulldown: d10-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (Y4) WKUP_GPIO0_51 */
AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7)
>;
};
d11_spi0_d0: d11-spi0-d0-pins {
pinctrl-single,pins = <
/* (Y3) MCU_SPI0_D0 */
AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0)
>;
};
d11_gpio: d11-gpio-pins {
pinctrl-single,pins = <
/* (Y3) WKUP_GPIO0_49 */
AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7)
>;
};
d11_gpio_pullup: d11-gpio-pullup-pins {
pinctrl-single,pins = <
/* (Y3) WKUP_GPIO0_49 */
AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7)
>;
};
d11_gpio_pulldown: d11-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (Y3) WKUP_GPIO0_49 */
AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7)
>;
};
d12_spi0_d1: d12-spi0-d1-pins {
pinctrl-single,pins = <
/* (Y2) MCU_SPI0_D1 */
AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0)
>;
};
d12_gpio: d12-gpio-pins {
pinctrl-single,pins = <
/* (Y2) WKUP_GPIO0_50 */
AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7)
>;
};
d12_gpio_pullup: d12-gpio-pullup-pins {
pinctrl-single,pins = <
/* (Y2) WKUP_GPIO0_50 */
AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7)
>;
};
d12_gpio_pulldown: d12-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (Y2) WKUP_GPIO0_50 */
AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7)
>;
};
d13_spi0_clk: d13-spi0-clk-pins {
pinctrl-single,pins = <
/* (Y1) MCU_SPI0_CLK */
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0)
>;
};
d13_gpio: d13-gpio-pins {
pinctrl-single,pins = <
/* (Y1) WKUP_GPIO0_48 */
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7)
>;
};
d13_gpio_pullup: d13-gpio-pullup-pins {
pinctrl-single,pins = <
/* (Y1) WKUP_GPIO0_48 */
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7)
>;
};
d13_gpio_pulldown: d13-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (Y1) WKUP_GPIO0_48 */
AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7)
>;
};
a0_gpio: a0-gpio-pins {
pinctrl-single,pins = <
/* (L6) WKUP_GPIO0_45 */
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7)
>;
};
a0_gpio_pullup: a0-gpio-pullup-pins {
pinctrl-single,pins = <
/* (L6) WKUP_GPIO0_45 */
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7)
>;
};
a0_gpio_pulldown: a0-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (L6) WKUP_GPIO0_45 */
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7)
>;
};
a1_gpio: a1-gpio-pins {
pinctrl-single,pins = <
/* (M6) WKUP_GPIO0_44 */
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7)
>;
};
a1_gpio_pullup: a1-gpio-pullup-pins {
pinctrl-single,pins = <
/* (M6) WKUP_GPIO0_44 */
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7)
>;
};
a1_gpio_pulldown: a1-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (M6) WKUP_GPIO0_44 */
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7)
>;
};
a2_gpio: a2-gpio-pins {
pinctrl-single,pins = <
/* (L5) WKUP_GPIO0_43 */
AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
>;
};
a2_gpio_pullup: a2-gpio-pullup-pins {
pinctrl-single,pins = <
/* (L5) WKUP_GPIO0_43 */
AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7)
>;
};
a2_gpio_pulldown: a2-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (L5) WKUP_GPIO0_43 */
AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7)
>;
};
a3_gpio: a3-gpio-pins {
pinctrl-single,pins = <
/* (M5) WKUP_GPIO0_39 */
AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
>;
};
a3_gpio_pullup: a3-gpio-pullup-pins {
pinctrl-single,pins = <
/* (M5) WKUP_GPIO0_39 */
AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7)
>;
};
a3_gpio_pulldown: a3-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (M5) WKUP_GPIO0_39 */
AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7)
>;
};
a4_gpio: a4-gpio-pins {
pinctrl-single,pins = <
/* (L2) WKUP_GPIO0_42 */
AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7)
>;
};
a4_gpio_pullup: a4-gpio-pullup-pins {
pinctrl-single,pins = <
/* (L2) WKUP_GPIO0_42 */
AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7)
>;
};
a4_gpio_pulldown: a4-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (L2) WKUP_GPIO0_42 */
AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7)
>;
};
a5_gpio: a5-gpio-pins {
pinctrl-single,pins = <
/* (N5) WKUP_GPIO0_35 */
AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7)
>;
};
a5_gpio_pullup: a5-gpio-pullup-pins {
pinctrl-single,pins = <
/* (N5) WKUP_GPIO0_35 */
AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7)
>;
};
a5_gpio_pulldown: a5-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (N5) WKUP_GPIO0_35 */
AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7)
>;
};
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
/* (AC7) WKUP_I2C0_SCL */
@ -136,23 +637,6 @@
>;
};
arduino_uart_pins_default: arduino-uart-default-pins {
pinctrl-single,pins = <
/* (P4) MCU_UART0_RXD */
AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)
/* (P5) MCU_UART0_TXD */
AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
>;
};
arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins {
pinctrl-single,pins = <
/* (P1) WKUP_GPIO0_31 */
AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
/* (N3) WKUP_GPIO0_33 */
AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7)
>;
};
arduino_io_oe_pins_default: arduino-io-oe-default-pins {
pinctrl-single,pins = <
@ -232,6 +716,220 @@
};
&main_pmx0 {
pinctrl-names =
"default",
"d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown",
"d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown",
"d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown",
"d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown",
"d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown",
"d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown";
pinctrl-0 = <&d4_ehrpwm0_a>;
pinctrl-1 = <&d4_ehrpwm0_a>;
pinctrl-2 = <&d4_gpio>;
pinctrl-3 = <&d4_gpio_pullup>;
pinctrl-4 = <&d4_gpio_pulldown>;
pinctrl-5 = <&d5_ehrpwm1_a>;
pinctrl-6 = <&d5_gpio>;
pinctrl-7 = <&d5_gpio_pullup>;
pinctrl-8 = <&d5_gpio_pulldown>;
pinctrl-9 = <&d6_ehrpwm2_a>;
pinctrl-10 = <&d6_gpio>;
pinctrl-11 = <&d6_gpio_pullup>;
pinctrl-12 = <&d6_gpio_pulldown>;
pinctrl-13 = <&d7_ehrpwm3_a>;
pinctrl-14 = <&d7_gpio>;
pinctrl-15 = <&d7_gpio_pullup>;
pinctrl-16 = <&d7_gpio_pulldown>;
pinctrl-17 = <&d8_ehrpwm4_a>;
pinctrl-18 = <&d8_gpio>;
pinctrl-19 = <&d8_gpio_pullup>;
pinctrl-20 = <&d8_gpio_pulldown>;
pinctrl-21 = <&d9_ehrpwm5_a>;
pinctrl-22 = <&d9_gpio>;
pinctrl-23 = <&d9_gpio_pullup>;
pinctrl-24 = <&d9_gpio_pulldown>;
d4_ehrpwm0_a: d4-ehrpwm0-a-pins {
pinctrl-single,pins = <
/* (AG18) EHRPWM0_A */
AM65X_IOPAD(0x0084, PIN_OUTPUT, 5)
>;
};
d4_gpio: d4-gpio-pins {
pinctrl-single,pins = <
/* (AG18) GPIO0_33 */
AM65X_IOPAD(0x0084, PIN_INPUT, 7)
>;
};
d4_gpio_pullup: d4-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AG18) GPIO0_33 */
AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7)
>;
};
d4_gpio_pulldown: d4-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AG18) GPIO0_33 */
AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7)
>;
};
d5_ehrpwm1_a: d5-ehrpwm1-a-pins {
pinctrl-single,pins = <
/* (AF17) EHRPWM1_A */
AM65X_IOPAD(0x008C, PIN_OUTPUT, 5)
>;
};
d5_gpio: d5-gpio-pins {
pinctrl-single,pins = <
/* (AF17) GPIO0_35 */
AM65X_IOPAD(0x008C, PIN_INPUT, 7)
>;
};
d5_gpio_pullup: d5-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AF17) GPIO0_35 */
AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7)
>;
};
d5_gpio_pulldown: d5-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AF17) GPIO0_35 */
AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7)
>;
};
d6_ehrpwm2_a: d6-ehrpwm2-a-pins {
pinctrl-single,pins = <
/* (AH16) EHRPWM2_A */
AM65X_IOPAD(0x0098, PIN_OUTPUT, 5)
>;
};
d6_gpio: d6-gpio-pins {
pinctrl-single,pins = <
/* (AH16) GPIO0_38 */
AM65X_IOPAD(0x0098, PIN_INPUT, 7)
>;
};
d6_gpio_pullup: d6-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AH16) GPIO0_38 */
AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7)
>;
};
d6_gpio_pulldown: d6-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AH16) GPIO0_38 */
AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7)
>;
};
d7_ehrpwm3_a: d7-ehrpwm3-a-pins {
pinctrl-single,pins = <
/* (AH15) EHRPWM3_A */
AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5)
>;
};
d7_gpio: d7-gpio-pins {
pinctrl-single,pins = <
/* (AH15) GPIO0_43 */
AM65X_IOPAD(0x00AC, PIN_INPUT, 7)
>;
};
d7_gpio_pullup: d7-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AH15) GPIO0_43 */
AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7)
>;
};
d7_gpio_pulldown: d7-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AH15) GPIO0_43 */
AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7)
>;
};
d8_ehrpwm4_a: d8-ehrpwm4-a-pins {
pinctrl-single,pins = <
/* (AG15) EHRPWM4_A */
AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5)
>;
};
d8_gpio: d8-gpio-pins {
pinctrl-single,pins = <
/* (AG15) GPIO0_48 */
AM65X_IOPAD(0x00C0, PIN_INPUT, 7)
>;
};
d8_gpio_pullup: d8-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AG15) GPIO0_48 */
AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7)
>;
};
d8_gpio_pulldown: d8-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AG15) GPIO0_48 */
AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7)
>;
};
d9_ehrpwm5_a: d9-ehrpwm5-a-pins {
pinctrl-single,pins = <
/* (AD15) EHRPWM5_A */
AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5)
>;
};
d9_gpio: d9-gpio-pins {
pinctrl-single,pins = <
/* (AD15) GPIO0_51 */
AM65X_IOPAD(0x00CC, PIN_INPUT, 7)
>;
};
d9_gpio_pullup: d9-gpio-pullup-pins {
pinctrl-single,pins = <
/* (AD15) GPIO0_51 */
AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7)
>;
};
d9_gpio_pulldown: d9-gpio-pulldown-pins {
pinctrl-single,pins = <
/* (AD15) GPIO0_51 */
AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7)
>;
};
main_pcie_enable_pins_default: main-pcie-enable-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
>;
};
main_uart1_pins_default: main-uart1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */
@ -273,17 +971,6 @@
>;
};
arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */
AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */
AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */
AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */
AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */
AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */
>;
};
dss_vout1_pins_default: dss-vout1-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */
@ -329,6 +1016,43 @@
AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
>;
};
icssg0_mdio_pins_default: icssg0-mdio-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
>;
};
icssg0_rgmii_pins_default: icssg0-rgmii-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
>;
};
};
&main_pmx1 {
@ -345,12 +1069,6 @@
AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
>;
};
ecap0_pins_default: ecap0-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
>;
};
};
&wkup_uart0 {
@ -366,13 +1084,9 @@
&mcu_uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&arduino_uart_pins_default>;
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>;
gpio-line-names =
"main_gpio0-base", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
@ -382,10 +1096,14 @@
"", "IO9";
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&main_pcie_enable_pins_default>;
};
&wkup_gpio0 {
pinctrl-names = "default";
pinctrl-0 =
<&arduino_io_d2_to_d3_pins_default>,
<&arduino_i2c_aio_switch_pins_default>,
<&arduino_io_oe_pins_default>,
<&push_button_pins_default>,
@ -547,13 +1265,8 @@
status = "disabled";
};
&ecap0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
&sdhci1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
@ -574,9 +1287,6 @@
&mcu_spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_spi0_pins_default>;
#address-cells = <1>;
#size-cells = <0>;
ti,pindir-d0-out-d1-in;
@ -716,3 +1426,21 @@
<&mcu_r5fss0_core1_memory_region>;
mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>;
};
&icssg0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&icssg0_mdio_pins_default>;
icssg0_eth0_phy: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
icssg0_eth1_phy: ethernet-phy@1 {
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};

16
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
View File

@ -449,6 +449,7 @@
ti,otap-del-sel-hs400 = <0x0>;
ti,trm-icp = <0x8>;
dma-coherent;
status = "disabled";
};
sdhci1: mmc@4fa0000 {
@ -471,6 +472,7 @@
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
status = "disabled";
};
scm_conf: scm-conf@100000 {
@ -498,8 +500,8 @@
};
dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 {
compatible = "syscon";
reg = <0x000041e0 0x14>;
compatible = "ti,am654-dss-oldi-io-ctrl", "syscon";
reg = <0x41e0 0x14>;
};
ehrpwm_tbclk: clock-controller@4140 {
@ -790,8 +792,12 @@
compatible = "ti,am654-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
<0x0 0x35000000 0x0 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x0 0x35000000 0x0 0x100000>,
<0x0 0x30b00000 0x0 0x10000>,
<0x0 0x30c00000 0x0 0x10000>,
<0x0 0x30d00000 0x0 0x8000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;
@ -1034,7 +1040,7 @@
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;

8
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
View File

@ -214,8 +214,12 @@
compatible = "ti,am654-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&inta_main_udmass>;
#dma-cells = <1>;

13
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
View File

@ -34,9 +34,16 @@
};
};
chipid@43000014 {
compatible = "ti,am654-chipid";
reg = <0x43000014 0x4>;
wkup_conf: bus@43000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x43000000 0x20000>;
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
wkup_pmx0: pinctrl@4301c000 {

74
arch/arm64/boot/dts/ti/k3-am652.dtsi Normal file
View File

@ -0,0 +1,74 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for AM65 SoC family in Dual core configuration
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am65.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0: cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&L2_0>;
};
};
L2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&msmc_l3>;
};
msmc_l3: l3-cache0 {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
thermal_zones: thermal-zones {
#include "k3-am654-industrial-thermal.dtsi"
};
};

16
arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
View File

@ -9,6 +9,7 @@
* Common bits of the IOT2050 Basic variant, PG1 and PG2
*/
#include "k3-am652.dtsi"
#include "k3-am65-iot2050-common.dtsi"
/ {
@ -17,21 +18,6 @@
/* 1G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
};
cpus {
cpu-map {
/delete-node/ cluster1;
};
/delete-node/ cpu@100;
/delete-node/ cpu@101;
};
/delete-node/ l2-cache1;
};
/* eMMC */
&sdhci0 {
status = "disabled";
};
&main_pmx0 {

2
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
View File

@ -449,6 +449,7 @@
};
&sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
bus-width = <8>;
@ -463,6 +464,7 @@
* disable sdhci1
*/
&sdhci1 {
status = "okay";
vmmc-supply = <&vdd_mmc1_sd>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;

2
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
View File

@ -11,6 +11,7 @@
/dts-v1/;
#include "k3-am654.dtsi"
#include "k3-am65-iot2050-common.dtsi"
/ {
@ -43,6 +44,7 @@
/* eMMC */
&sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
bus-width = <8>;

12
arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts
View File

@ -27,12 +27,6 @@
};
&main_pmx0 {
main_m2_enable_pins_default: main-m2-enable-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */
>;
};
main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins {
pinctrl-single,pins = <
AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */
@ -66,15 +60,13 @@
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 =
<&main_m2_pcie_mux_control>,
<&arduino_io_d4_to_d9_pins_default>;
pinctrl-0 = <&main_m2_pcie_mux_control>;
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 =
<&main_m2_enable_pins_default>,
<&main_pcie_enable_pins_default>,
<&main_pmx0_m2_config_pins_default>,
<&main_pmx1_m2_config_pins_default>,
<&cp2102n_reset_pin_default>;

1
arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
View File

@ -31,6 +31,7 @@
can1 = &mcu_mcan1;
can2 = &main_mcan6;
can3 = &main_mcan7;
ethernet0 = &cpsw_port1;
};
vusb_main: regulator-vusb-main5v0 {

96
arch/arm64/boot/dts/ti/k3-am69-sk.dts
View File

@ -433,6 +433,13 @@
&wkup_pmx2 {
bootph-all;
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
/* (AA37) MCU_ADC1_AIN4.WKUP_GPIO0_83 */
J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 7)
>;
};
wkup_uart0_pins_default: wkup-uart0-default-pins {
bootph-all;
pinctrl-single,pins = <
@ -631,6 +638,93 @@
compatible = "atmel,24c512";
reg = <0x51>;
};
tps659413: pmic@48 {
compatible = "ti,tps6594-q1";
reg = <0x48>;
system-power-controller;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&wkup_gpio0>;
interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
ti,primary-pmic;
buck12-supply = <&vsys_3v3>;
buck3-supply = <&vsys_3v3>;
buck4-supply = <&vsys_3v3>;
buck5-supply = <&vsys_3v3>;
ldo1-supply = <&vsys_3v3>;
ldo2-supply = <&vsys_3v3>;
ldo3-supply = <&vsys_3v3>;
ldo4-supply = <&vsys_3v3>;
regulators {
bucka12: buck12 {
regulator-name = "vdd_ddr_1v1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
bucka3: buck3 {
regulator-name = "vdd_ram_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
bucka4: buck4 {
regulator-name = "vdd_io_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
bucka5: buck5 {
regulator-name = "vdd_mcu_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldoa1: ldo1 {
regulator-name = "vdd_mcuio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa2: ldo2 {
regulator-name = "vdd_mcuio_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldoa3: ldo3 {
regulator-name = "vds_dll_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa4: ldo4 {
regulator-name = "vda_mcu_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&wkup_gpio0 {
@ -671,7 +765,7 @@
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
"IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#",
"IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz",
"PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz",

9
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
View File

@ -281,8 +281,12 @@
compatible = "ti,j721e-navss-main-udmap";
reg = <0x00 0x31150000 0x00 0x100>,
<0x00 0x34000000 0x00 0x100000>,
<0x00 0x35000000 0x00 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x00 0x35000000 0x00 0x100000>,
<0x00 0x30b00000 0x00 0x4000>,
<0x00 0x30c00000 0x00 0x4000>,
<0x00 0x30d00000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;
@ -647,6 +651,7 @@
ti,otap-del-sel-hs400 = <0x5>;
ti,itap-del-sel-legacy = <0x10>;
ti,itap-del-sel-mmc-hs = <0xa>;
ti,itap-del-sel-ddr52 = <0x3>;
ti,strobe-sel = <0x77>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;

21
arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
View File

@ -178,9 +178,16 @@
};
};
chipid@43000014 {
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
wkup_conf: bus@43000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
@ -346,8 +353,12 @@
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
<0x00 0x2aa00000 0x00 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x00 0x2aa00000 0x00 0x40000>,
<0x00 0x284a0000 0x00 0x4000>,
<0x00 0x284c0000 0x00 0x4000>,
<0x00 0x28400000 0x00 0x2000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;

153
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
View File

@ -127,6 +127,14 @@
};
};
&wkup_pmx3 {
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (E18) WKUP_GPIO0_84 */
>;
};
};
&main_pmx0 {
main_i2c0_pins_default: main-i2c0-default-pins {
pinctrl-single,pins = <
@ -264,6 +272,151 @@
compatible = "atmel,24c256";
reg = <0x50>;
};
tps659414: pmic@48 {
compatible = "ti,tps6594-q1";
reg = <0x48>;
system-power-controller;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&wkup_gpio0>;
interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
ti,primary-pmic;
buck1-supply = <&vsys_3v3>;
buck2-supply = <&vsys_3v3>;
buck3-supply = <&vsys_3v3>;
buck4-supply = <&vsys_3v3>;
buck5-supply = <&vsys_3v3>;
ldo1-supply = <&vsys_3v3>;
ldo2-supply = <&vsys_3v3>;
ldo3-supply = <&vsys_3v3>;
ldo4-supply = <&vsys_3v3>;
regulators {
bucka1: buck1 {
regulator-name = "vda_mcu_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
bucka2: buck2 {
regulator-name = "vdd_mcuio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
bucka3: buck3 {
regulator-name = "vdd_mcu_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
bucka4: buck4 {
regulator-name = "vdd_ddr_1v1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
bucka5: buck5 {
regulator-name = "vdd_phyio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa1: ldo1 {
regulator-name = "vdd1_lpddr4_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa2: ldo2 {
regulator-name = "vda_dll_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa3: ldo3 {
regulator-name = "vdd_wk_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa4: ldo4 {
regulator-name = "vda_pll_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
lp876441: pmic@4c {
compatible = "ti,lp8764-q1";
reg = <0x4c>;
system-power-controller;
interrupt-parent = <&wkup_gpio0>;
interrupts = <84 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
buck1-supply = <&vsys_3v3>;
buck2-supply = <&vsys_3v3>;
buck3-supply = <&vsys_3v3>;
buck4-supply = <&vsys_3v3>;
regulators: regulators {
buckb1: buck1 {
regulator-name = "vdd_cpu_avs";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-boot-on;
bootph-pre-ram;
};
buckb2: buck2 {
regulator-name = "vdd_ram_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
buckb3: buck3 {
regulator-name = "vdd_core_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
buckb4: buck4 {
regulator-name = "vdd_io_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&ospi0 {

53
arch/arm64/boot/dts/ti/k3-j721e-evm-pcie0-ep.dtso Normal file
View File

@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0
/**
* DT Overlay for enabling PCIE0 instance in Endpoint Configuration with the
* J7 common processor board.
*
* J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/*
* Since Root Complex and Endpoint modes are mutually exclusive
* disable Root Complex mode.
*/
&pcie0_rc {
status = "disabled";
};
&cbass_main {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic500>;
pcie0_ep: pcie-ep@2900000 {
compatible = "ti,j721e-pcie-ep";
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
max-link-speed = <3>;
num-lanes = <1>;
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 239 1>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
};
};

8
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
View File

@ -382,8 +382,12 @@
compatible = "ti,j721e-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x100000>,
<0x0 0x35000000 0x0 0x100000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x0 0x35000000 0x0 0x100000>,
<0x0 0x30b00000 0x0 0x20000>,
<0x0 0x30c00000 0x0 0x10000>,
<0x0 0x30d00000 0x0 0x8000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;

21
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
View File

@ -48,9 +48,16 @@
};
};
chipid@43000014 {
compatible = "ti,am654-chipid";
reg = <0x0 0x43000014 0x0 0x4>;
wkup_conf: bus@43000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
wkup_pmx0: pinctrl@4301c000 {
@ -468,8 +475,12 @@
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;

151
arch/arm64/boot/dts/ti/k3-j721e-sk.dts
View File

@ -459,6 +459,12 @@
};
&wkup_pmx0 {
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
>;
};
mcu_cpsw_pins_default: mcu-cpsw-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
@ -560,6 +566,151 @@
compatible = "atmel,24c512";
reg = <0x51>;
};
tps659413: pmic@48 {
compatible = "ti,tps6594-q1";
reg = <0x48>;
system-power-controller;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&wkup_gpio0>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
ti,primary-pmic;
buck123-supply = <&vsys_3v3>;
buck4-supply = <&vsys_3v3>;
buck5-supply = <&vsys_3v3>;
ldo1-supply = <&vsys_3v3>;
ldo2-supply = <&vsys_3v3>;
ldo3-supply = <&vsys_3v3>;
ldo4-supply = <&vsys_3v3>;
regulators {
bucka123: buck123 {
regulator-name = "vdd_cpu_avs";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
bootph-pre-ram;
};
bucka4: buck4 {
regulator-name = "vdd_mcu_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
bucka5: buck5 {
regulator-name = "vdd_phyio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa1: ldo1 {
regulator-name = "vdd1_lpddr4_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa2: ldo2 {
regulator-name = "vdd_mcuio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa3: ldo3 {
regulator-name = "vdda_dll_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa4: ldo4 {
regulator-name = "vda_mcu_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
tps659411: pmic@4c {
compatible = "ti,tps6594-q1";
reg = <0x4c>;
system-power-controller;
interrupt-parent = <&wkup_gpio0>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
buck1234-supply = <&vsys_3v3>;
buck5-supply = <&vsys_3v3>;
ldo1-supply = <&vsys_3v3>;
ldo2-supply = <&vsys_3v3>;
ldo3-supply = <&vsys_3v3>;
ldo4-supply = <&vsys_3v3>;
regulators {
buckb1234: buck1234 {
regulator-name = "vdd_core_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
buckb5: buck5 {
regulator-name = "vdd_ram_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldob1: ldo1 {
regulator-name = "vdd_sd_dv";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldob2: ldo2 {
regulator-name = "vdd_usb_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldob3: ldo3 {
regulator-name = "vdd_io_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldob4: ldo4 {
regulator-name = "vda_pll_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&mcu_uart0 {

160
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi
View File

@ -152,6 +152,12 @@
>;
};
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0d4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */
>;
};
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
@ -199,6 +205,160 @@
compatible = "atmel,24c256";
reg = <0x50>;
};
tps659413: pmic@48 {
compatible = "ti,tps6594-q1";
reg = <0x48>;
system-power-controller;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&wkup_gpio0>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
ti,primary-pmic;
buck12-supply = <&vsys_3v3>;
buck3-supply = <&vsys_3v3>;
buck4-supply = <&vsys_3v3>;
buck5-supply = <&vsys_3v3>;
ldo1-supply = <&vsys_3v3>;
ldo2-supply = <&vsys_3v3>;
ldo3-supply = <&vsys_3v3>;
ldo4-supply = <&vsys_3v3>;
regulators {
bucka12: buck12 {
regulator-name = "vdd_cpu_avs";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
bootph-pre-ram;
};
bucka3: buck3 {
regulator-name = "vdd_mcu_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
bucka4: buck4 {
regulator-name = "vdd_ddr_1v1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
bucka5: buck5 {
regulator-name = "vdd_phyio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa1: ldo1 {
regulator-name = "vdd1_lpddr4_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa2: ldo2 {
regulator-name = "vdd_mcuio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa3: ldo3 {
regulator-name = "vdda_dll_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa4: ldo4 {
regulator-name = "vda_mcu_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
tps659411: pmic@4c {
compatible = "ti,tps6594-q1";
reg = <0x4c>;
system-power-controller;
interrupt-parent = <&wkup_gpio0>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
buck1234-supply = <&vsys_3v3>;
buck5-supply = <&vsys_3v3>;
ldo1-supply = <&vsys_3v3>;
ldo2-supply = <&vsys_3v3>;
ldo3-supply = <&vsys_3v3>;
ldo4-supply = <&vsys_3v3>;
regulators {
buckb1234: buck1234 {
regulator-name = "vdd_core_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
buckb5: buck5 {
regulator-name = "vdd_ram_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldob1: ldo1 {
regulator-name = "vdd_sd_dv";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldob2: ldo2 {
regulator-name = "vdd_usb_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldob3: ldo3 {
regulator-name = "vdd_io_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldob4: ldo4 {
regulator-name = "vda_pll_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&ospi0 {

53
arch/arm64/boot/dts/ti/k3-j721s2-evm-pcie1-ep.dtso Normal file
View File

@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0
/**
* DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the
* J7 common processor board.
*
* J7 Common Processor Board Product Link: https://www.ti.com/tool/J721EXCPXEVM
*
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/*
* Since Root Complex and Endpoint modes are mutually exclusive
* disable Root Complex mode.
*/
&pcie1_rc {
status = "disabled";
};
&cbass_main {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic500>;
pcie1_ep: pcie-ep@2910000 {
compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x00 0x18000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
max-link-speed = <3>;
num-lanes = <1>;
power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 276 41>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
};
};

9
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
View File

@ -766,6 +766,7 @@
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,itap-del-sel-ddr50 = <0x2>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
@ -1086,8 +1087,12 @@
compatible = "ti,j721e-navss-main-udmap";
reg = <0x0 0x31150000 0x0 0x100>,
<0x0 0x34000000 0x0 0x80000>,
<0x0 0x35000000 0x0 0x200000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x0 0x35000000 0x0 0x200000>,
<0x0 0x30b00000 0x0 0x20000>,
<0x0 0x30c00000 0x0 0x8000>,
<0x0 0x30d00000 0x0 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;

21
arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
View File

@ -34,9 +34,16 @@
};
};
chipid@43000014 {
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
wkup_conf: bus@43000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
secure_proxy_sa3: mailbox@43600000 {
@ -471,8 +478,12 @@
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x2aa00000 0x0 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;

193
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi
View File

@ -172,6 +172,15 @@
};
};
&wkup_pmx1 {
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
/* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7)
>;
};
};
&wkup_pmx2 {
wkup_i2c0_pins_default: wkup-i2c0-default-pins {
pinctrl-single,pins = <
@ -208,6 +217,190 @@
compatible = "atmel,24c256";
reg = <0x50>;
};
tps659411: pmic@48 {
compatible = "ti,tps6594-q1";
reg = <0x48>;
system-power-controller;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&wkup_gpio0>;
interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
ti,primary-pmic;
buck1234-supply = <&vsys_3v3>;
buck5-supply = <&vsys_3v3>;
ldo1-supply = <&vsys_3v3>;
ldo2-supply = <&vsys_3v3>;
ldo3-supply = <&vsys_3v3>;
ldo4-supply = <&vsys_3v3>;
regulators {
bucka1234: buck1234 {
regulator-name = "vdd_cpu_avs";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
bootph-pre-ram;
};
bucka5: buck5 {
regulator-name = "vdd_mcu_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldoa1: ldo1 {
regulator-name = "vdd_mcuwk_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa2: ldo2 {
regulator-name = "vdd_mcu_gpioret_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldoa3: ldo3 {
regulator-name = "vdd_mcuio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa4: ldo4 {
regulator-name = "vda_mcu_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
tps659414: pmic@4c {
compatible = "ti,tps6594-q1";
reg = <0x4c>;
system-power-controller;
interrupt-parent = <&wkup_gpio0>;
interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
buck1-supply = <&vsys_3v3>;
buck2-supply = <&vsys_3v3>;
buck3-supply = <&vsys_3v3>;
buck4-supply = <&vsys_3v3>;
buck5-supply = <&vsys_3v3>;
ldo1-supply = <&vsys_3v3>;
ldo2-supply = <&vsys_3v3>;
ldo3-supply = <&vsys_3v3>;
ldo4-supply = <&vsys_3v3>;
regulators {
buckb1: buck1 {
regulator-name = "vdd_io_1v8_reg";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
buckb2: buck2 {
regulator-name = "vdd_fpd_1v1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
buckb3: buck3 {
regulator-name = "vdd_phy_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buckb4: buck4 {
regulator-name = "vdd_ddr_1v1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
buckb5: buck5 {
regulator-name = "vdd_ram_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldob1: ldo1 {
regulator-name = "vdd_wk_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldob2: ldo2 {
regulator-name = "vdd_gpioret_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldob3: ldo3 {
regulator-name = "vda_dll_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldob4: ldo4 {
regulator-name = "vda_pll_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
lp876411: pmic@58 {
compatible = "ti,lp8764-q1";
reg = <0x58>;
system-power-controller;
interrupt-parent = <&wkup_gpio0>;
interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
buck1234-supply = <&vsys_3v3>;
regulators {
buckc1234: buck1234 {
regulator-name = "vdd_core_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&main_i2c0 {

102
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
View File

@ -273,6 +273,10 @@
};
};
&wkup_gpio0 {
status = "okay";
};
&main_pmx0 {
bootph-all;
main_uart8_pins_default: main-uart8-default-pins {
@ -407,6 +411,17 @@
};
};
&wkup_pmx1 {
status = "okay";
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
/* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7)
>;
};
};
&wkup_pmx0 {
bootph-all;
mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
@ -471,6 +486,93 @@
compatible = "atmel,24c256";
reg = <0x50>;
};
tps659413: pmic@48 {
compatible = "ti,tps6594-q1";
reg = <0x48>;
system-power-controller;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&wkup_gpio0>;
interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
gpio-controller;
#gpio-cells = <2>;
ti,primary-pmic;
buck12-supply = <&vsys_3v3>;
buck3-supply = <&vsys_3v3>;
buck4-supply = <&vsys_3v3>;
buck5-supply = <&vsys_3v3>;
ldo1-supply = <&vsys_3v3>;
ldo2-supply = <&vsys_3v3>;
ldo3-supply = <&vsys_3v3>;
ldo4-supply = <&vsys_3v3>;
regulators {
bucka12: buck12 {
regulator-name = "vdd_ddr_1v1";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
bucka3: buck3 {
regulator-name = "vdd_ram_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
bucka4: buck4 {
regulator-name = "vdd_io_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
bucka5: buck5 {
regulator-name = "vdd_mcu_0v85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldoa1: ldo1 {
regulator-name = "vdd_mcuio_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa2: ldo2 {
regulator-name = "vdd_mcuio_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldoa3: ldo3 {
regulator-name = "vds_dll_0v8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
ldoa4: ldo4 {
regulator-name = "vda_mcu_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&mcu_uart0 {

9
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
View File

@ -712,6 +712,7 @@
ti,itap-del-sel-sd-hs = <0x0>;
ti,itap-del-sel-sdr12 = <0x0>;
ti,itap-del-sel-sdr25 = <0x0>;
ti,itap-del-sel-ddr50 = <0x2>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
@ -1188,8 +1189,12 @@
compatible = "ti,j721e-navss-main-udmap";
reg = <0x00 0x31150000 0x00 0x100>,
<0x00 0x34000000 0x00 0x80000>,
<0x00 0x35000000 0x00 0x200000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x00 0x35000000 0x00 0x200000>,
<0x00 0x30b00000 0x00 0x20000>,
<0x00 0x30c00000 0x00 0x8000>,
<0x00 0x30d00000 0x00 0x4000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;

22
arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi
View File

@ -38,10 +38,18 @@
};
};
chipid@43000014 {
wkup_conf: bus@43000000 {
bootph-all;
compatible = "ti,am654-chipid";
reg = <0x00 0x43000014 0x00 0x4>;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x43000000 0x20000>;
chipid: chipid@14 {
bootph-all;
compatible = "ti,am654-chipid";
reg = <0x14 0x4>;
};
};
secure_proxy_sa3: mailbox@43600000 {
@ -478,8 +486,12 @@
compatible = "ti,j721e-navss-mcu-udmap";
reg = <0x00 0x285c0000 0x00 0x100>,
<0x00 0x2a800000 0x00 0x40000>,
<0x00 0x2aa00000 0x00 0x40000>;
reg-names = "gcfg", "rchanrt", "tchanrt";
<0x00 0x2aa00000 0x00 0x40000>,
<0x00 0x284a0000 0x00 0x4000>,
<0x00 0x284c0000 0x00 0x4000>,
<0x00 0x28400000 0x00 0x2000>;
reg-names = "gcfg", "rchanrt", "tchanrt",
"tchan", "rchan", "rflow";
msi-parent = <&main_udmass_inta>;
#dma-cells = <1>;