IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
If a mux clock is initialised (by hardware or firmware) with an
invalid parent, its ->get_parent() can return an out of range
index. For example, the generic mux clock attempts to return
-EINVAL, which due to the u8 return type ends up a rather large
number. Using this index with the parent_names[] array results
in an invalid pointer and (usually) a crash in the following
strcmp().
This patch adds a check for the parent index being in range,
ignoring clocks reporting invalid values.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Tested-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the GDSC instances that exist as part of apq8084 MMCC block.
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the GDSC instances that exist as part of apq8084 GCC block
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add the GDSC instances that exist as part of msm8974 MMCC block
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
There's just one GDSC as part of the msm8974 GCC block.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add all data for the GDSCs which are part of msm8916 GCC block.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Certain devices can have GDSCs' which support ON as the only state.
They can't be power collapsed to either hit RET or OFF.
The clients drivers for these GDSCs' however would expect the state
of the core to be reset following a GDSC disable and re-enable.
To do this assert/deassert reset lines every time the client
driver would request the GDSC to be powered on/off instead.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Along with the GDSC power switch, there is additional control
to either retain all memory (core and peripheral) within a given
powerdomain or to turn them off while the GDSC is powered down.
Add support for these by modelling a RET state where all
memory is retained and an OFF state where all memory gets turned
off.
The controls provided are granular enough to be able to support
various differnt levels of RET states, like a 'shallow RET' with all memory
retained and a 'deep RET' with some memory retained while some others
are lost. The current patch does not support this and considers
just one RET state where all memory is retained. Futher work, if
needed can support multiple different levels of RET state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The common clk probe registers a clk provider and a reset controller.
Update it to register a genpd provider using the gdsc data provided
by each platform.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
GDSCs (Global Distributed Switch Controllers) are responsible for
safely collapsing and restoring power to peripherals in the SoC.
These are best modelled as power domains using genpd and given
the registers are scattered throughout the clock controller register
space, its best to have the support added through the clock driver.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
On 32-bit architectures, 'unsigned long' (the type used to hold clock
rates, in Hz) is often only 32 bits wide. DIV_ROUND_UP() (as used in,
e.g., commit b11d282dbea2 "clk: divider: fix rate calculation for
fractional rates") can yield an integer overflow on clock rates that are
not (by themselves) too large to fit in 32 bits, because it performs
addition before the division. See for example:
DIV_ROUND_UP(3000000000, 1500000000) = (3.0G + 1.5G - 1) / 1.5G
= OVERFLOW / 1.5G
This patch fixes such cases by always promoting the dividend to 64-bits
(unsigned long long) before doing the division. While this patch does
not resolve the issue with large clock rates across the common clock
framework nor address the problems with doing full 64-bit arithmetic on
a 32-bit architecture, it does fix some issues seen when using clock
dividers on a 3GHz reference clock to produce a 1.5GHz CPU clock for an
ARMv7 Brahma B15 SoC.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reference: http://lkml.kernel.org/g/20150413201433.GQ32500@ld-irv-0074
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This platform driver has a OF device ID table but the OF module
alias information is not created so module autoloading won't work.
Signed-off-by: Luis de Bethencourt <luis@debethencourt.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
In the error path of at91_clk_register_system(), sys->irq is freed
unconditionally but it may not exist or be request at all.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
at91_pmc_read is a workaround to allow external drivers to acces some
registers of the PMC. There is no need for it in clk-utmi.c as we aready
have a pointer to the struct at91_pmc.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Sometimes the display driver may want to change the parent PLL of
the display clocks (byte and pixel clocks) depending on the
use-case. Currently the parent is fixed by means of having a
frequency table with one entry that chooses a particular parent.
Remove this restriction and use the parent the clock is
configured for in the hardware during clk_set_rate(). This
requires consumers to rely on the default parent or to configure
the parent with clk_set_parent()/assigned-clock-parents on the
clocks before calling clk_set_rate().
Tested-by: Archit Taneja <architt@codeaurora.org>
Cc: Hai Li <hali@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The OPP list needs to be protected against concurrent accesses. Using
simple RCU read locks does the trick and gets rid of the following
lockdep warning:
===============================
[ INFO: suspicious RCU usage. ]
4.2.0-next-20150908 #1 Not tainted
-------------------------------
drivers/base/power/opp.c:460 Missing rcu_read_lock() or dev_opp_list_lock protection!
other info that might help us debug this:
rcu_scheduler_active = 1, debug_locks = 0
4 locks held by kworker/u8:0/6:
#0: ("%s""deferwq"){++++.+}, at: [<c0040d8c>] process_one_work+0x118/0x4bc
#1: (deferred_probe_work){+.+.+.}, at: [<c0040d8c>] process_one_work+0x118/0x4bc
#2: (&dev->mutex){......}, at: [<c03b8194>] __device_attach+0x20/0x118
#3: (prepare_lock){+.+...}, at: [<c054bc08>] clk_prepare_lock+0x10/0xf8
stack backtrace:
CPU: 2 PID: 6 Comm: kworker/u8:0 Not tainted 4.2.0-next-20150908 #1
Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
Workqueue: deferwq deferred_probe_work_func
[<c001802c>] (unwind_backtrace) from [<c00135a4>] (show_stack+0x10/0x14)
[<c00135a4>] (show_stack) from [<c02a8418>] (dump_stack+0x94/0xd4)
[<c02a8418>] (dump_stack) from [<c03c6f6c>] (dev_pm_opp_find_freq_ceil+0x108/0x114)
[<c03c6f6c>] (dev_pm_opp_find_freq_ceil) from [<c0551a3c>] (dfll_calculate_rate_request+0xb8/0x170)
[<c0551a3c>] (dfll_calculate_rate_request) from [<c0551b10>] (dfll_clk_round_rate+0x1c/0x2c)
[<c0551b10>] (dfll_clk_round_rate) from [<c054de2c>] (clk_calc_new_rates+0x1b8/0x228)
[<c054de2c>] (clk_calc_new_rates) from [<c054e44c>] (clk_core_set_rate_nolock+0x44/0xac)
[<c054e44c>] (clk_core_set_rate_nolock) from [<c054e4d8>] (clk_set_rate+0x24/0x34)
[<c054e4d8>] (clk_set_rate) from [<c0512460>] (tegra124_cpufreq_probe+0x120/0x230)
[<c0512460>] (tegra124_cpufreq_probe) from [<c03b9cbc>] (platform_drv_probe+0x44/0xac)
[<c03b9cbc>] (platform_drv_probe) from [<c03b84c8>] (driver_probe_device+0x218/0x304)
[<c03b84c8>] (driver_probe_device) from [<c03b69b0>] (bus_for_each_drv+0x60/0x94)
[<c03b69b0>] (bus_for_each_drv) from [<c03b8228>] (__device_attach+0xb4/0x118)
ata1: SATA link down (SStatus 0 SControl 300)
[<c03b8228>] (__device_attach) from [<c03b77c8>] (bus_probe_device+0x88/0x90)
[<c03b77c8>] (bus_probe_device) from [<c03b7be8>] (deferred_probe_work_func+0x58/0x8c)
[<c03b7be8>] (deferred_probe_work_func) from [<c0040dfc>] (process_one_work+0x188/0x4bc)
[<c0040dfc>] (process_one_work) from [<c004117c>] (worker_thread+0x4c/0x4f4)
[<c004117c>] (worker_thread) from [<c0047230>] (kthread+0xe4/0xf8)
[<c0047230>] (kthread) from [<c000f7d0>] (ret_from_fork+0x14/0x24)
Signed-off-by: Thierry Reding <treding@nvidia.com>
Fixes: c4fe70ada40f ("clk: tegra: Add closed loop support for the DFLL")
[vince.h@nvidia.com: Unlock rcu on error path]
Signed-off-by: Vince Hsu <vince.h@nvidia.com>
[sboyd@codeaurora.org: Dropped second hunk that nested the rcu
read lock unnecessarily]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
The new determine_rate prototype allows for clock rates exceeding
2^31-1 Hz to be used. Switch the DFLL clock to use determine_rate
instead of round_rate and unlock the top rates supported by the
Tegra124.
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: Thierry Reding <treding@nvidia.com>
FSYS0 fixed clocks are not added to fsys0_cmu_info, this makes
some of the usb clocks orphans. This fixes the same.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_FSYS1 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys1_200.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_FSYS0 clocks names to match with user manual.
And also adds missing gate clock for aclk_fsys0_200.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_PERIS clocks names to match with user manual.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_PERIC1 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric1_66.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_PERIC0 clocks names to match with user manual.
And also adds missing gate clock for aclk_peric0_66.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_CCORE clocks names to match with user manual.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_TOP1 clocks names to match with user manual.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch renames CMU_TOP0 clocks names to match with user manual.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This adds some of the missing GATE clocks of CMU_TOPC block.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Corrects the CMU_TOPC block clock names as per user manual.
This does not change any functionalities.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
nr_clk_ids for FSYS1 block is wrongly set as TOP1 block,
this patch corrects it.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch corrects the nr_clk_ids for fsys0 block
which is wrongly set to number of clocks of the TOP1 CMU.
This also adjusts the gate clocks order.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
and the GATE clocks are at bit 16 in their respective registers.
For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1.
And their DIV and GATE clks are in xxx_TOP1_FSYS11 instead of TOP1_FSYS1.
This patch corrects it.
This also adds xxx_FSYS11 to be saved/restore during s2r cycles.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Corrects the bit width of DIV_TOPC3 register.
These are wrongly set to 3 which should be 4 bit wide as per UM.
This also adjusts the MUX clock order.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
handful of patches to add more critical clocks on rockchip SoCs that
are affected by newly introduced gpio clock handling.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABCAAGBQJV9yQdAAoJENidgRMleOc9Nt4P/1C1+9QilU/VsPjfyMPtgzla
d4O55sd7isSzbM51tNPGw+j48CFAMS4u7yE6bjAnxVeo/Y0KD7K51V5/j1D1EZL8
xqVjxcA4bTRcvlEvHlozvuhe69hVvUpwtBFfDw2VvQVMF24yGTgpu9tQQG4Vgb9x
+DLUjyDGxT/tc6jKalC4hZlwHW/PqRJA5xlO5IULkrazSnGM5OrhgfyQgEJDDEto
pzi6bRTzkYXecnVOkXQZTFsBbgBEOGsv1M9QfMAlVW8MiQzO+go1/jWoTMFT2BFT
DWtV/Ry0EH/+NGsAE650PaQG2RVLtn9kLt1Unpk25RYhaivCdsX6e2YyptFPLM0D
pkXN+TL7eZ+KujrvFZFw7J7f/j6gmsZEOmoHZGuY87G6h45GTgMFuqutZBkTCAAW
1Me+3p5J6z83VXrzEd53t1fVYbdgjvHyAer3Smxf8Ihl5jl6bhrJUiMl3l50OZ5h
8Ji8QbA3mTFZ10CaaDkDTHa44RWmuGPsIfgVTAq0+XHqigxhTVm6nOJG6EyFVCo2
5F3eQvwr8g1oChi+hZO/VzmPsr9TceNL4jdWIC/HDPzuaCUt0MzbE9auuK0JzRAa
tn1LbvmiOtaUPI59XSfv1qzhXWYSS8qt7hkG3cQncTpwdZahAKFH61/ooatN+Jr6
aFYSKSMfB3Aa+fldjrCS
=Y9Y4
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"A couple build fixes for drivers introduced in the merge window and a
handful of patches to add more critical clocks on rockchip SoCs that
are affected by newly introduced gpio clock handling"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: rockchip: Add pclk_peri to critical clocks on RK3066/RK3188
clk: rockchip: add pclk_cpu to the list of rk3188 critical clocks
clk: rockchip: handle critical clocks after registering all clocks
clk: Hi6220: separately build stub clock driver
clk: h8s2678: Fix compile error
Again a result of the gpio-clock-liberation the rk3368 needs the
pclk_pd_pmu marked as critical, to boot successfully.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This is a collection of a few late fixes and other misc. stuff that
had dependencies on things being merged from other trees.
The bulk of the changes are for samsung/exynos SoCs for some changes
that needed a few minor reworks so ended up a bit late. The others
are mainly for qcom SoCs: a couple fixes and some DTS updates.
There's one conflict with drivers/cpufreq/exynos-cpufreq.c because
it's now been completely removed, but there were some fixes that hit
mainline in the meantime.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIbBAABAgAGBQJV8fkAAAoJEFk3GJrT+8Zllf8P9jj3+TnvbJS/8bWoQoB7BRUZ
LZPgi2+sBXylrBV60uQdyodiTHQUMZhbL7GvgEVG0z6yyin7nyijqNkulTbQbWmg
WhumLNCNcs8vlZegA/corbwgcVC7FkjOP97HveTe2mgwZ+GaXj9qMRQzBsMqSXEo
4890ZeP1nWBTP42oXOQHkNyKWFBjuERK0dTw2MXj7WE0/Ag8i7ERp76uJQdQ7V5O
BpNRwxp3vSCky8rxbpD/avWdlspv1yZGBQyLeIreVq2YQFojvT36K8wHcf6iWBT/
pzGGV/uZM7MnrGZdqSfVEMDHl7Z2s7Ls+sv5F6Md7ErnVDerHGRjw/6lJDjbeH7u
trucpsuhz5yhTjpZssGHH2NT8pWxxh8M+AaNOiiH8PuYESAbPAmWLpWkn+648bIn
P++Z90DIyfNEqnNSMHkcQYpVt8zc4g75gZfTIIsXLB+DLgzgSK8ergrfyRN/O0zj
oFY35g3wHdgisnGve+BAW30zTZtP19TMT36OltWjIkjuRZC29PS2vkH8eTETdVXx
01f/qcpbB1L1rXfIBjNkjx81j89XPd68JIBfctTF5QBOAGm/Dix6tj2mU/N7TNu5
TrBmD3CXdOQbCPaoK/qWX7/b11IN/XOlGL06hhYwbSdvCVy7rNccApXvfnrDWziK
Ly923FP1OB7h0Kk1cmo=
=85Ck
-----END PGP SIGNATURE-----
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull late ARM SoC updates from Kevin Hilman:
"This is a collection of a few late fixes and other misc stuff that had
dependencies on things being merged from other trees.
The bulk of the changes are for samsung/exynos SoCs for some changes
that needed a few minor reworks so ended up a bit late. The others
are mainly for qcom SoCs: a couple fixes and some DTS updates"
* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits)
ARM: multi_v7_defconfig: Enable PBIAS regulator
soc: qcom: smd: Correct fBLOCKREADINTR handling
soc: qcom: smd: Use correct remote processor ID
soc: qcom: smem: Fix errant private access
ARM: dts: qcom: msm8974-sony-xperia-honami: Use stdout-path
ARM: dts: qcom: msm8960-cdp: Use stdout-path
ARM: dts: qcom: msm8660-surf: Use stdout-path
ARM: dts: qcom: ipq8064-ap148: Use stdout-path
ARM: dts: qcom: apq8084-mtp: Use stdout-path
ARM: dts: qcom: apq8084-ifc6540: Use stdout-path
ARM: dts: qcom: apq8074-dragonboard: Use stdout-path
ARM: dts: qcom: apq8064-ifc6410: Use stdout-path
ARM: dts: qcom: apq8064-cm-qs600: Use stdout-path
ARM: dts: qcom: Label serial nodes for aliasing and stdout-path
reset: ath79: Fix missing spin_lock_init
reset: Add (devm_)reset_control_get stub functions
ARM: EXYNOS: switch to using generic cpufreq driver for exynos4x12
cpufreq: exynos: Remove unselectable rule for arm-exynos-cpufreq.o
ARM: dts: add iommu property to JPEG device for exynos4
ARM: dts: enable SPI1 for exynos4412-odroidu3
...
Now that the rockchip clock subsystem does clock gating with GPIO banks,
these are no longer enabled once during probe and no longer stay enabled
for eternity. When all these clocks are disabled, the parent clock pclk_peri
might be disabled too, as no other child claims it. So, we need to add pclk_peri
to the critical clocks.
Signed-off-by: Romain Perier <romain.perier@gmail.com>
Tested-by: Michael Niewoehner <linux@mniewoehner.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
pclk_cpu needs to keep running because it is needed for devices like
the act8865 regulator but with the recent gpio clock handling this is
not always the case anymore. So add it to the list of critical clocks.
Signed-off-by: Michael Niewoehner <linux@mniewoehner.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently the registration of critical clocks is done in the function
shared between rk3066 and rk3188 clock trees. That results in them
getting handled maybe before all of them are registered.
Therefore move the critical clock handling down to the end of the soc-
specific clock registration function, so that all clocks are registered
before they're maybe handled as critical clock.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Michael Niewoehner <linux@mniewoehner.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Pull i2c updates from Wolfram Sang:
"Features:
- new drivers: Renesas EMEV2, register based MUX, NXP LPC2xxx
- core: scans DT and assigns wakeup interrupts. no driver changes needed.
- core: some refcouting issues fixed and better API for that
- core: new helper function for best effort block read emulation
- slave framework: proper DT bindings and userspace instantiation
- some bigger work for xiic, pxa, omap drivers
.. and quite a number of smaller driver fixes, cleanups, improvements"
* 'i2c/for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (65 commits)
i2c: mux: reg Change ioread endianness for readback
i2c: mux: reg: fix compilation warnings
i2c: mux: reg: simplify register size checking
i2c: muxes: fix leaked i2c adapter device node references
i2c: allow specifying separate wakeup interrupt in device tree
of/irq: export of_get_irq_byname()
i2c: xgene-slimpro: dma_mapping_error() doesn't return an error code
i2c: Replace I2C_CROS_EC_TUNNEL dependency
eeprom: at24: use i2c_smbus_read_i2c_block_data_or_emulated
i2c: core: Add support for best effort block read emulation
i2c: lpc2k: add driver
i2c: mux: Add register-based mux i2c-mux-reg
i2c: dt: describe generic bindings
i2c: slave: print warning if slave flag not set
i2c: support 10 bit and slave addresses in sysfs 'new_device'
i2c: take address space into account when checking for used addresses
i2c: apply DT flags when probing
i2c: make address check indpendent from client struct
i2c: rename address check functions
i2c: apply address offset for slaves, too
...
cycle
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing
all call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a
combined call to irq_set_chained_handler_and_data(). This
series was created by Thomas Gleixner after the problem was
observed by Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which
is way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs
from IRQ numbers. The goal is to get rid of the irq number
from the handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw
spinlocks in IRQ handlers to play nice with the realtime
patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8,
PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner
sun4i driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC
subdrivers.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJV6YzgAAoJEEEQszewGV1zbIAQAILzMrzWkxsy7bhvL4QdP5/K
OG3EodE//AE0G5gKugUDjg5t2lftdiIJVhjDA17ruETCSciuAxZSLThlMy1sQgyN
LPxy9LlCrmsqrYt9+fmJ9js8j52RBJikKK0RUyUVz0VojTBplRpElyEx/KxwM5sG
Hy3+hU61uKO0j9AyIcsa/RKP6SGavwZdHytJBsHNw+pODyE3UZCf52ChAVBsTPfE
MV70g3Qzfqur7ZFqcNgtUV7qCyYvlF12ooiihrGFDOsTL3sSq4/OXB7z1z1mGGHL
Dgq8pXJ6EIZlCbk+jFMTzPRSzy46dxNai0eErjTUVEldH1tOphzGMvKmOdm/nczH
4M/UOWOKBE1aOYZNPtnUgDy2MRt5K9VJStCNSHEQCB2lGdojNAtmj2cmr8flBN5m
gM9FDpIS1/C+OYYTkOY9ftPsH5zOk7sCLEHSH5USYRGJHihzLnkV90eiN6a7vlF1
hyTGrIyl6e//E5JBgamjnR3+fYuxQGr6WeAZEP/gXZRm7BCKCaPwCarq+kPZVG4A
nolZ/QQN6XYPSlveSPU97VYvLYEUvXaKN0Hf2DTbwkqvNFp7JORD65QLESPtQoIp
x95iHMdB/1+0OfgOqMmlOtKpOKREeQ/R+KWACxsrr5Rfv3/7CP4BMRGypIZ/iPmz
HWoyDI4lIebBR+JnjMjK
=4QFX
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.3 development
cycle.
Like with GPIO it's a lot of stuff. If my subsystems are any sign of
the overall tempo of the kernel v4.3 will be a gigantic diff.
[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
we'll see - Linus ]
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing all
call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a combined
call to irq_set_chained_handler_and_data(). This series was
created by Thomas Gleixner after the problem was observed by
Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which is
way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs from
IRQ numbers. The goal is to get rid of the irq number from the
handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
in IRQ handlers to play nice with the realtime patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner sun4i
driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC subdrivers"
* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
pinctrl: at91: fix null pointer dereference
pinctrl: mediatek: Implement wake handler and suspend resume
pinctrl: mediatek: Fix multiple registration issue.
pinctrl: sh-pfc: r8a7794: add USB pin groups
pinctrl: at91: Use generic irq_{request,release}_resources()
pinctrl: cherryview: Use raw_spinlock for locking
pinctrl: baytrail: Use raw_spinlock for locking
pinctrl: imx6ul: Remove .owner field
pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pinctrl: sun4i: add spdif to pin description.
pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
pinctrl: baytrail: Serialize all register access
pinctrl: baytrail: Drop FSF mailing address
pinctrl: rockchip: only enable gpio clock when it setting
pinctrl/mediatek: fix spelling mistake in dev_err error message
pinctrl: cherryview: Serialize all register access
pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
pinctrl: nomadik: reflect current input value
...
The previous code, kernel builds Hi6220's common clock driver and stub
clock driver together. Stub clock driver has introduced the dependency
with CONFIG_MAILBOX, so kernel will not build Hi6220's common clock
driver due ARM64's defconfig have not enabled CONFIG_MAILBOX by default.
So separately build stub clock driver and common clock driver for
Hi6220; and only let stub clock driver has the dependency with
CONFIG_MAILBOX.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Recent cleanup removed some include files without checking if the cleaned
up code still compiles. This results in the following compile error.
drivers/clk/h8300/clk-h8s2678.c: In function ‘h8s2678_pll_clk_setup’:
drivers/clk/h8300/clk-h8s2678.c:99:14: error:
implicit declaration of function ‘kzalloc’
drivers/clk/h8300/clk-h8s2678.c:138:2: error:
implicit declaration of function ‘kfree’
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This is the usual large batch of DT updates. Lots and lots of smaller
changes, some of the larger ones to point out are:
- Rockchip veyron (Chromebook) support, as well as several other new boards
- DRM support on Atmel AT91SAM9N12EK
- USB additions on some Allwinner platforms
- Mediatek MT6580 support
- Freescale i.MX6UL support
- Cleanups for Renesas shmobile platforms
- Lots of added devices on LPC18xx
- Lots of added devices and boards on UniPhier
There's also some dependent code added here, in particular some branches
that are primarily merged through the clock tree.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJV5OMWAAoJEIwa5zzehBx3r2QP/1skn0zzgfvbK0kkPOh9q3Jk
jX1elN4Wde1SnScz8UbdVb9nmdbhxsuYE/3+Lz7yCndWScBiak4qcsNHrSRhh3FA
ST7Ub8DLc2TxY9K7eDkyVCcNkP35+UQTHCN76R5Lgrlfw3UO9Zr3xPFX3+Kd6aWz
9X8UnvJacQQIN/vO6J02kB96sKPEIANfuMgO6vDSbmcZ1RrdlHzjoRwAV0smECtJ
NyOh+NQdPBR0gSl/peyKzAXoDHNXpDotltTmIz3tPA+dYBO/qG//B73H/oqox0ql
AKAktyaDzdxXEuixPtAroo4dDy3xuIQ6xU+DNhPWQq0BgaxHWqkwq60d74ot8vCz
8gvC8pwA6gavbqVFNePOnwPNSyWZX01scX4fp903NjVM8/rGPvCR4y6p8lFIyVkG
P0L8rmY/UYq3fieaAb1W0odASDrQpgg3zsHD7to43hz6jaRnMRCpA8nTVqJcyHqI
E6YfGQH87Kpbvkjo0FYqo5P6xCCRTq+QUys6JruNYg05R/gd8AG7cXaVNO3yvg3T
lRwNXDBt/zcp2exKnGR0IdGMUMICzsuoB8ZePkQdIWwePrd4AzT5qYJe/txmg1rd
q+9VJqQkeF+txLd9XUV2W/Hcuzu3ZPCbs97I9tTKQHMGwKUZaPfuk2r4+4K+Ps5a
dYwdms39p6AIT43rK+m3
=D2Pm
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"Ladies and gentlemen, we proudly announce to you the latest branch of
ARM device tree contents for the mainline kernel. Come and see, come
and see!
No less than twentythree thousand lines of additions! Just imagine the
joy you will have of using your mainline kernel on newly supported
hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or
UniPhier hardware!
For those of you feeling less adventurous, added hardware support on
platforms such as TI DM814x and Gumstix Overo platforms might be more
of your liking.
We've got something for everyone here!
Ahem. Cough. So, anyway...
This is the usual large batch of DT updates. Lots and lots of smaller
changes, some of the larger ones to point out are:
- Rockchip veyron (Chromebook) support, as well as several other new boards
- DRM support on Atmel AT91SAM9N12EK
- USB additions on some Allwinner platforms
- Mediatek MT6580 support
- Freescale i.MX6UL support
- cleanups for Renesas shmobile platforms
- lots of added devices on LPC18xx
- lots of added devices and boards on UniPhier
There's also some dependent code added here, in particular some
branches that are primarily merged through the clock tree"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits)
ARM: tegra: Add gpio-ranges property
ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
ARM: tegra: Add Tegra124 PMU support
ARM: tegra: jetson-tk1: Add GK20A GPU DT node
ARM: tegra: venice2: Add GK20A GPU DT node
ARM: tegra: Add IOMMU node to GK20A
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Enable the DFLL on the Jetson TK1
ARM: tegra: Add the DFLL to Tegra124 device tree
ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
ARM: dts: rockchip: correct regulator power states for suspend
ARM: dts: rockchip: correct regulator PM properties
ARM: dts: vexpress: Use assigned-clock-parents for sp810
pinctrl: tegra: Only set the gpio range if needed
arm: boot: dts: am4372: add ARM timers and SCU nodes
ARM: dts: AM4372: Add the am4372-rtc compatible string
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
...
Some releases this branch is nearly empty, others we have more stuff. It
tends to gather drivers that need SoC modification or dependencies such
that they have to (also) go in through our tree.
For this release, we have merged in part of the reset controller tree
(with handshake that the parts we have merged in will remain stable),
as well as dependencies on a few clock branches.
In general, new items here are:
- Qualcomm driver for SMM/SMD, which is how they communicate with the
coprocessors on (some) of their platforms
- Memory controller work for ARM's PL172 memory controller
- Reset drivers for various platforms
- PMU power domain support for Marvell platforms
- Tegra support for T132/T210 SoCs: PMC, fuse, memory controller per-SoC support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJV5Ou9AAoJEIwa5zzehBx3/k4P/jA5CVNiDvIs0GoTR3uGOuec
MYd19oKf76reV1oL5bBSpg9uryJd3fPzK0JC/qU3pYfsCVFp2TWZD7liNpitqHyt
2xL02gzJQgjHzL3QrxTQrOFJDO6P8Vm2k/5pI0KX1beoulHvI+iHejNryXGjSKSx
9vbs1GPXU9IV831YOHSaMmHz727J65bbZE8Up113ctT+WbEIc1g/ihKzUgi/8xXW
RniMxGsX8HynE3VH+UBDMbY6XkOmzZa1Wabgll735MXwIUFG1+TsvHNuGehXUski
ySwqk67en25i0F/Q7oobLSZwCPbA6Ylxk9aOfr0AnAqOEKwgKWS+K7HkEiNMz7yh
nt22b5SVkQ80sTCbNEkdJajOZ8oRalUae19CGxvMfVh77LmQ2sRI9iJrwXcxkt8W
ASs6uDDAUNC5pIWfjeJE50vsDr//Hed/WtsIjenYOtb+RI1kru5iTTgp4oLPBiy5
OeHxOfiL7gPvyZQbuPgMKAGdoGBsa/7wTM7KWJCMP6mPGHpShO8XUUsuljqKHm4w
nBV7eZRMiIuWkjRKw4bjp7R0NVKR5sOfAkZhjCsXB0aqA/NU2zyNbViWcGCh6yj8
3beZ93SdEdrKX6N8pPiAhGTMFA6eev8YeUHO7kM4IhC91ILjHlPpCs1pYk3pwEkO
ABC7GyMY6Olg1pZJweEa
=B6jn
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson:
"Some releases this branch is nearly empty, others we have more stuff.
It tends to gather drivers that need SoC modification or dependencies
such that they have to (also) go in through our tree.
For this release, we have merged in part of the reset controller tree
(with handshake that the parts we have merged in will remain stable),
as well as dependencies on a few clock branches.
In general, new items here are:
- Qualcomm driver for SMM/SMD, which is how they communicate with the
coprocessors on (some) of their platforms
- memory controller work for ARM's PL172 memory controller
- reset drivers for various platforms
- PMU power domain support for Marvell platforms
- Tegra support for T132/T210 SoCs: PMC, fuse, memory controller
per-SoC support"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (49 commits)
ARM: tegra: cpuidle: implement cpuidle_state.enter_freeze()
ARM: tegra: Disable cpuidle if PSCI is available
soc/tegra: pmc: Use existing pclk reference
soc/tegra: pmc: Remove unnecessary return statement
soc: tegra: Remove redundant $(CONFIG_ARCH_TEGRA) in Makefile
memory: tegra: Add Tegra210 support
memory: tegra: Add support for a variable-size client ID bitfield
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: Add CPG/MSTP Clock Domain support
ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets
reset: reset-zynq: Adding support for Xilinx Zynq reset controller.
docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings.
MIPS: ath79: Add the reset controller to the AR9132 dtsi
reset: Add a driver for the reset controller on the AR71XX/AR9XXX
devicetree: Add bindings for the ATH79 reset controller
reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property
doc: dt: add documentation for lpc1850-rgu reset driver
...
