Commit Graph

8611 Commits

Author SHA1 Message Date
Linus Torvalds
36001a2fa6 The clk core gains a new set of APIs that allow drivers to both acquire clks
and prepare and enable them at the same time. This also comes with devm support
 so that drivers can make a single call to get and prepare and enable the clk
 and have that all undone when their driver is removed. Many folks have
 requested this feature over the years, but we've had disagreements about how to
 implement it and if it was worthwhile to encourage drivers to use such an API.
 Now it's here, so let's see how it goes. I hope that by introducing this API we
 can identify drivers that would benefit from further consolidation of clk API
 usage, possibly by moving such logic to the bus layer and out of drivers
 altogether.
 
 Outside of that major API update, we have the usual collection of driver
 updates. A few new SoCs are supported, mostly Qualcomm and Renesas this time
 around. Then we have the long tail of non-critical fixes and minor feature
 additions to various clk drivers. And finally more clk provider migration to
 struct clk_parent_data, reducing boot times in the process.
 
 Core:
  - devm helpers for clk_get() + clk_prepare() and clk_enable()
 
 New Drivers:
  - Support for the camera clock controller in Qualcomm SM8450 and
    the display and gpu clock controllers in Qualcomm SM8350
  - Add support for the Renesas RZ/Five SoC
 
 Updates:
  - Various fixes, new clocks and USB GDSCs are introduced for Qualcomm IPQ8074
  - Fixes to Qualcomm MSM8939 for issues introduced by inheriting the MSM8916
    GCC driver
  - Support for a new type of voteable GDSCs used by Qualcomm SC8280XP PCIe
    GDSCs
  - Qualcomm SC8280XP pipe clocks transitioned to the new phy-mux implementation
  - Qualcomm MSM8996 GCC, RPM clock driver and some clocks in MSM8994 GCC are
    migrated to use clk_parent_data
  - Corrected the topology for Titan (camera) GDSCs on Qualcomm SDM845 and
    SM8250
  - Qualcomm MSM8916 gains more possible frequencies for its GP clocks.
  - The GCC and tsens handling on Qualcomm MSM8960 is reworked to mimic the
    design in IPQ8074 to allow the GCC driver to probe earlier.
  - The regulator based mmcx supply for Qualcomm dispcc and videocc is dropped,
    as the only upstream target that adapted this interface was transitioned
    several kernel versions ago
  - Qualcomm GDSCs found to be enabled at boot will now reflect in the enable
    count of the supply, as was done with the regulator supplies previously
  - Correct adc1, nic_media and edma1's parents for NXP i.MX93
  - rdiv, mfd values, the return rate in recalc_rate and add more frequencies in
    the table for fracn-gppll on i.MX
  - Remove Allwinner workaround logic/compatible in fixed factor code
  - MediaTek clk driver cleanups
  - Add reset support to more MediaTek clk drivers
  - deduplicate Allwinner ccu_clks arrays
  - Allwinner H6 GPU DFS support
  - Adjust Allwinner Kconfig to limit choice
  - Fix initconst confusion on Renesas R-Car Gen4
  - Add GPT/POEG (PWM) clocks and resets on Renesas RZ/G2L
  - Add PFC and WDT clocks and resets on Renesas RZ/V2M
  - Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
    Renesas R-Car S4-8
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The clk core gains a new set of APIs that allow drivers to both
  acquire clks and prepare and enable them at the same time. This also
  comes with devm support so that drivers can make a single call to get
  and prepare and enable the clk and have that all undone when their
  driver is removed.

  Many folks have requested this feature over the years, but we've had
  disagreements about how to implement it and if it was worthwhile to
  encourage drivers to use such an API.

  Now it's here, so let's see how it goes.

  I hope that by introducing this API we can identify drivers that would
  benefit from further consolidation of clk API usage, possibly by
  moving such logic to the bus layer and out of drivers altogether.

  Outside of that major API update, we have the usual collection of
  driver updates. A few new SoCs are supported, mostly Qualcomm and
  Renesas this time around. Then we have the long tail of non-critical
  fixes and minor feature additions to various clk drivers.

  And finally more clk provider migration to struct clk_parent_data,
  reducing boot times in the process.

  Summary:

  Core:

   - devm helpers for clk_get() + clk_prepare() and clk_enable()

  New Drivers:

   - Support for the camera clock controller in Qualcomm SM8450 and the
     display and gpu clock controllers in Qualcomm SM8350

   - Add support for the Renesas RZ/Five SoC

  Updates:

   - Various fixes, new clocks and USB GDSCs are introduced for Qualcomm
     IPQ8074

   - Fixes to Qualcomm MSM8939 for issues introduced by inheriting the
     MSM8916 GCC driver

   - Support for a new type of voteable GDSCs used by Qualcomm SC8280XP
     PCIe GDSCs

   - Qualcomm SC8280XP pipe clocks transitioned to the new phy-mux
     implementation

   - Qualcomm MSM8996 GCC, RPM clock driver and some clocks in MSM8994
     GCC are migrated to use clk_parent_data

   - Corrected the topology for Titan (camera) GDSCs on Qualcomm SDM845
     and SM8250

   - Qualcomm MSM8916 gains more possible frequencies for its GP clocks.

   - The GCC and tsens handling on Qualcomm MSM8960 is reworked to mimic
     the design in IPQ8074 to allow the GCC driver to probe earlier.

   - The regulator based mmcx supply for Qualcomm dispcc and videocc is
     dropped, as the only upstream target that adapted this interface
     was transitioned several kernel versions ago

   - Qualcomm GDSCs found to be enabled at boot will now reflect in the
     enable count of the supply, as was done with the regulator supplies
     previously

   - Correct adc1, nic_media and edma1's parents for NXP i.MX93

   - rdiv, mfd values, the return rate in recalc_rate and add more
     frequencies in the table for fracn-gppll on i.MX

   - Remove Allwinner workaround logic/compatible in fixed factor code

   - MediaTek clk driver cleanups

   - Add reset support to more MediaTek clk drivers

   - deduplicate Allwinner ccu_clks arrays

   - Allwinner H6 GPU DFS support

   - Adjust Allwinner Kconfig to limit choice

   - Fix initconst confusion on Renesas R-Car Gen4

   - Add GPT/POEG (PWM) clocks and resets on Renesas RZ/G2L

   - Add PFC and WDT clocks and resets on Renesas RZ/V2M

   - Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
     Renesas R-Car S4-8"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (124 commits)
  clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()
  clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()
  clk: divider: Introduce devm_clk_hw_register_divider_parent_hw()
  clk: qcom: gcc-msm8994: use parent_hws for gpll0/4
  clk: qcom: clk-rpm: convert to parent_data API
  dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc
  clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies
  clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies
  clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies
  clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions
  clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock
  clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk
  clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled
  clk: qcom: Drop mmcx gdsc supply for dispcc and videocc
  clk: qcom: fix build error initializer element is not constant
  clk: sprd: Add dt-bindings include file for UMS512
  dt-bindings: clk: sprd: Add bindings for ums512 clock controller
  clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS
  dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources
  clk: qcom: add support for SM8350 DISPCC
  ...
2022-08-04 18:40:08 -07:00
Linus Torvalds
5f0848190c platform-drivers-x86 for v6.0-1
Highlights:
  -  Microsoft Surface:
     - SSAM hot unplug support
     - Surface Pro 8 keyboard cover support
     - Tablet mode switch support for Surface Pro 8 and Surface Laptop Studio
  -  thinkpad_acpi: AMD Automatice Mode Transitions (AMT) support
  -  Mellanox:
     - Vulcan chassis COMe NVSwitch management support
     - XH3000 support
  - New generic/shared Intel P2SB (Primary to Sideband) support
  - Lots of small cleanups
  - Various small bugfixes
  - Various new hardware ids / quirks additions
 
 The following is an automated git shortlog grouped by driver:
 
 ACPI:
  -  video: Fix acpi_video_handles_brightness_key_presses()
  -  video: Change how we determine if brightness key-presses are handled
 
 Documentation/ABI:
  -  Add new attributes for mlxreg-io sysfs interfaces
  -  mlxreg-io: Fix contact info
 
 Drop the PMC_ATOM Kconfig option:
  - Drop the PMC_ATOM Kconfig option
 
 EDAC, pnd2:
  -  convert to use common P2SB accessor
  -  Use proper I/O accessors and address space annotation
 
 HID:
  -  surface-hid: Add support for hot-removal
 
 ISST:
  -  PUNIT device mapping with Sub-NUMA clustering
 
 Kconfig:
  -  Remove unnecessary "if X86"
 
 MAINTAINERS:
  -  repair file entry in MICROSOFT SURFACE AGGREGATOR TABLET-MODE SWITCH
 
 Merge tag 'ib-mfd-edac-i2c-leds-pinctrl-platform-watchdog-v5.20' into review-hans:
  - Merge tag 'ib-mfd-edac-i2c-leds-pinctrl-platform-watchdog-v5.20' into review-hans
 
 Move AMD platform drivers to separate directory:
  - Move AMD platform drivers to separate directory
 
 acer-wmi:
  -  Use backlight helper
 
 acer_wmi:
  -  Cleanup Kconfig selects
 
 apple-gmux:
  -  Use backlight helper
 
 asus-wmi:
  -  Add mic-mute LED classdev support
  -  Add key mappings
 
 compal-laptop:
  -  Use backlight helper
 
 efi:
  -  Fix efi_power_off() not being run before acpi_power_off() when necessary
 
 gigabyte-wmi:
  -  add support for B660I AORUS PRO DDR4
 
 hp-wmi:
  -  Ignore Sanitization Mode event
 
 i2c:
  -  i801: convert to use common P2SB accessor
 
 ideapad-laptop:
  -  Add Ideapad 5 15ITL05 to ideapad_dytc_v4_allow_table[]
  -  Add allow_v4_dytc module parameter
 
 intel/pmc:
  -  Add Alder Lake N support to PMC core driver
 
 intel_atomisp2_led:
  -  Also turn off the always-on camera LED on the Asus T100TAF
 
 leds:
  -  simatic-ipc-leds-gpio: Add GPIO version of Siemens driver
  -  simatic-ipc-leds: Convert to use P2SB accessor
 
 mfd:
  -  lpc_ich: Add support for pinctrl in non-ACPI system
  -  lpc_ich: Switch to generic p2sb_bar()
  -  lpc_ich: Factor out lpc_ich_enable_spi_write()
 
 mlx-platform:
  -  Add COME board revision register
  -  Add support for new system XH3000
  -  Introduce support for COMe NVSwitch management module for Vulcan chassis
  -  Add support for systems equipped with two ASICs
  -  Add cosmetic changes for alignment
  -  Make activation of some drivers conditional
 
 p2sb:
  -  Move out of X86_PLATFORM_DEVICES dependency
 
 panasonic-laptop:
  -  Use acpi_video_get_backlight_type()
  -  filter out duplicate volume up/down/mute keypresses
  -  don't report duplicate brightness key-presses
  -  revert "Resolve hotkey double trigger bug"
  -  sort includes alphabetically
  -  de-obfuscate button codes
 
 pinctrl:
  -  intel: Check against matching data instead of ACPI companion
 
 platform/mellanox:
  -  mlxreg-lc: Fix error flow and extend verbosity
  -  mlxreg-io: Add locking for io operations
  -  nvsw-sn2201: fix error code in nvsw_sn2201_create_static_devices()
 
 platform/olpc:
  -  Fix uninitialized data in debugfs write
 
 platform/surface:
  -  gpe: Add support for 13" Intel version of Surface Laptop 4
  -  tabletsw: Fix __le32 integer access
  -  Update copyright year of various drivers
  -  aggregator: Move subsystem hub drivers to their own module
  -  aggregator: Move device registry helper functions to core module
  -  aggregator_registry: Add support for tablet mode switch on Surface Laptop Studio
  -  aggregator_registry: Add support for tablet mode switch on Surface Pro 8
  -  Add KIP/POS tablet-mode switch driver
  -  aggregator: Add helper macros for requests with argument and return value
  -  aggregator: Reserve more event- and target-categories
  -  avoid flush_scheduled_work() usage
  -  aggregator_registry: Add support for keyboard cover on Surface Pro 8
  -  aggregator_registry: Add KIP device hub
  -  aggregator_registry: Change device ID for base hub
  -  aggregator_registry: Generify subsystem hub functionality
  -  aggregator: Add comment for KIP subsystem category
  -  aggregator_registry: Use client device wrappers for notifier registration
  -  aggregator: Allow notifiers to avoid communication on unregistering
  -  aggregator: Allow devices to be marked as hot-removed
  -  aggregator: Allow is_ssam_device() to be used when CONFIG_SURFACE_AGGREGATOR_BUS is disabled
 
 platform/x86/amd/pmc:
  -  Add new platform support
  -  Add new acpi id for PMC controller
 
 platform/x86/dell:
  -  Kconfig: Remove unnecessary "depends on X86_PLATFORM_DEVICES"
 
 platform/x86/intel:
  -  Add Primary to Sideband (P2SB) bridge support
 
 platform/x86/intel/ifs:
  -  Mark as BROKEN
 
 platform/x86/intel/pmt:
  -  telemetry: Fix fixed region handling
 
 platform/x86/intel/vsec:
  -  Fix wrong type for local status variables
  -  Add PCI error recovery support to Intel PMT
  -  Add support for Raptor Lake
  -  Rework early hardware code
 
 pmc_atom:
  -  Fix comment typo
  -  Match all Lex BayTrail boards with critclk_systems DMI table
 
 power/supply:
  -  surface_battery: Use client device wrappers for notifier registration
  -  surface_charger: Use client device wrappers for notifier registration
 
 serial-multi-instantiate:
  -  Sort ACPI IDs by HID
  -  Get rid of redundant 'else'
  -  Use while (i--) pattern to clean up
  -  Improve dev_err_probe() messaging
  -  Drop duplicate check
  -  Improve autodetection
 
 simatic-ipc:
  -  drop custom P2SB bar code
 
 sony-laptop:
  -  Remove useless comparisons in sony_pic_read_possible_resource()
 
 system76_acpi:
  -  Use dev_get_drvdata
 
 thinkpad_acpi:
  -  Enable AMT by default on supported systems
  -  Add support for hotkey 0x131a
  -  Add support for automatic mode transitions
  -  profile capabilities as integer
  -  do not use PSC mode on Intel platforms
  -  Fix a memory leak of EFCH MMIO resource
  -  Replace custom str_on_off() etc
  -  Sort headers for better maintenance
  -  Use backlight helper
 
 tools/power/x86/intel-speed-select:
  -  Remove unneeded semicolon
  -  Fix off by one check
 
 watchdog:
  -  simatic-ipc-wdt: convert to use P2SB accessor
 
 x86-android-tablets:
  -  Fix Lenovo Yoga Tablet 2 830/1050 poweroff again
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Merge tag 'platform-drivers-x86-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86

Pull x86 platform driver updates from Hans de Goede:

 - Microsoft Surface:
     - SSAM hot unplug support
     - Surface Pro 8 keyboard cover support
     - Tablet mode switch support for Surface Pro 8 and Surface Laptop
       Studio

 - thinkpad_acpi:
     - AMD Automatice Mode Transitions (AMT) support

 - Mellanox:
     - Vulcan chassis COMe NVSwitch management support
     - XH3000 support

 - New generic/shared Intel P2SB (Primary to Sideband) support

 - Lots of small cleanups

 - Various small bugfixes

 - Various new hardware ids / quirks additions

* tag 'platform-drivers-x86-v6.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86: (105 commits)
  platform/x86/intel/vsec: Fix wrong type for local status variables
  platform/x86: p2sb: Move out of X86_PLATFORM_DEVICES dependency
  platform/x86: pmc_atom: Fix comment typo
  platform/surface: gpe: Add support for 13" Intel version of Surface Laptop 4
  platform/olpc: Fix uninitialized data in debugfs write
  platform/mellanox: mlxreg-lc: Fix error flow and extend verbosity
  platform/x86: pmc_atom: Match all Lex BayTrail boards with critclk_systems DMI table
  platform/x86: sony-laptop: Remove useless comparisons in sony_pic_read_possible_resource()
  tools/power/x86/intel-speed-select: Remove unneeded semicolon
  tools/power/x86/intel-speed-select: Fix off by one check
  platform/surface: tabletsw: Fix __le32 integer access
  Documentation/ABI: Add new attributes for mlxreg-io sysfs interfaces
  Documentation/ABI: mlxreg-io: Fix contact info
  platform/mellanox: mlxreg-io: Add locking for io operations
  platform/x86: mlx-platform: Add COME board revision register
  platform/x86: mlx-platform: Add support for new system XH3000
  platform/x86: mlx-platform: Introduce support for COMe NVSwitch management module for Vulcan chassis
  platform/x86: mlx-platform: Add support for systems equipped with two ASICs
  platform/x86: mlx-platform: Add cosmetic changes for alignment
  platform/x86: mlx-platform: Make activation of some drivers conditional
  ...
2022-08-04 18:19:14 -07:00
Linus Torvalds
c1c76700a0 SPDX changes for 6.0-rc1
Here is the set of SPDX comment updates for 6.0-rc1.
 
 Nothing huge here, just a number of updated SPDX license tags and
 cleanups based on the review of a number of common patterns in GPLv2
 boilerplate text.  Also included in here are a few other minor updates,
 2 USB files, and one Documentation file update to get the SPDX lines
 correct.
 
 All of these have been in the linux-next tree for a very long time.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx

Pull SPDX updates from Greg KH:
 "Here is the set of SPDX comment updates for 6.0-rc1.

  Nothing huge here, just a number of updated SPDX license tags and
  cleanups based on the review of a number of common patterns in GPLv2
  boilerplate text.

  Also included in here are a few other minor updates, two USB files,
  and one Documentation file update to get the SPDX lines correct.

  All of these have been in the linux-next tree for a very long time"

* tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx: (28 commits)
  Documentation: samsung-s3c24xx: Add blank line after SPDX directive
  x86/crypto: Remove stray comment terminator
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_406.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_398.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_391.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_390.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_385.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_319.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_318.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_298.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_292.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_179.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 2)
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 1)
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_160.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_152.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_149.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_147.RULE
  treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_133.RULE
  ...
2022-08-04 12:12:54 -07:00
Linus Torvalds
665fe72a7d linux-kselftest-kunit-5.20-rc1
This KUnit update for Linux 5.20-rc1 consists of several fixes and an
 important feature to discourage running KUnit tests on production
 systems. Running tests on a production system could leave the system
 in a bad state. This new feature adds:
 
 - adds a new taint type, TAINT_TEST to signal that a test has been run.
   This should discourage people from running these tests on production
   systems, and to make it easier to tell if tests have been run
   accidentally (by loading the wrong configuration, etc.)
 
 - several documentation and tool enhancements and fixes.
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Merge tag 'linux-kselftest-kunit-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest

Pull KUnit updates from Shuah Khan:
 "This consists of several fixes and an important feature to discourage
  running KUnit tests on production systems. Running tests on a
  production system could leave the system in a bad state.

  Summary:

   - Add a new taint type, TAINT_TEST to signal that a test has been
     run.

     This should discourage people from running these tests on
     production systems, and to make it easier to tell if tests have
     been run accidentally (by loading the wrong configuration, etc)

   - Several documentation and tool enhancements and fixes"

* tag 'linux-kselftest-kunit-5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest: (29 commits)
  Documentation: KUnit: Fix example with compilation error
  Documentation: kunit: Add CLI args for kunit_tool
  kcsan: test: Add a .kunitconfig to run KCSAN tests
  kunit: executor: Fix a memory leak on failure in kunit_filter_tests
  clk: explicitly disable CONFIG_UML_PCI_OVER_VIRTIO in .kunitconfig
  mmc: sdhci-of-aspeed: test: Use kunit_test_suite() macro
  nitro_enclaves: test: Use kunit_test_suite() macro
  thunderbolt: test: Use kunit_test_suite() macro
  kunit: flatten kunit_suite*** to kunit_suite** in .kunit_test_suites
  kunit: unify module and builtin suite definitions
  selftest: Taint kernel when test module loaded
  module: panic: Taint the kernel when selftest modules load
  Documentation: kunit: fix example run_kunit func to allow spaces in args
  Documentation: kunit: Cleanup run_wrapper, fix x-ref
  kunit: test.h: fix a kernel-doc markup
  kunit: tool: Enable virtio/PCI by default on UML
  kunit: tool: make --kunitconfig repeatable, blindly concat
  kunit: add coverage_uml.config to enable GCOV on UML
  kunit: tool: refactor internal kconfig handling, allow overriding
  kunit: tool: introduce --qemu_args
  ...
2022-08-02 19:34:45 -07:00
Stephen Boyd
08fc500fe3 Merge branch 'clk-allwinner' into clk-next
* clk-allwinner:
  clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS
  clk: sunxi: Do not select the PRCM MFD
  clk: sunxi: Limit legacy clocks to 32-bit ARM
  clk: sunxi-ng: Deduplicate ccu_clks arrays
2022-08-02 12:20:51 -07:00
Stephen Boyd
dfcbbd73dd Merge branches 'clk-renesas', 'clk-spreadtrum', 'clk-imx' and 'clk-qcom' into clk-next
* clk-renesas: (22 commits)
  clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config
  clk: renesas: r9a07g043: Add support for RZ/Five SoC
  dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions
  clk: renesas: r8a779f0: Add HSCIF clocks
  clk: renesas: r8a779f0: Add PCIe clocks
  clk: renesas: r8a779f0: Add Z0 and Z1 clock support
  dt-bindings: clock: renesas,rzg2l: Simplify header file references
  clk: renesas: rza1: Remove struct rz_cpg
  clk: renesas: r8a7779: Remove struct r8a7779_cpg
  clk: renesas: r8a7778: Remove struct r8a7778_cpg
  clk: renesas: sh73a0: Remove sh73a0_cpg.reg
  clk: renesas: r8a7740: Remove r8a7740_cpg.reg
  clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg
  clk: renesas: r8a779f0: Add SDHI0 clock
  clk: renesas: r8a779f0: Add thermal clock
  clk: renesas: rzg2l: Fix reset status function
  clk: renesas: r9a06g032: Fix UART clkgrp bitsel
  clk: renesas: r9a06g032: Drop some unused fields
  clk: renesas: r9a09g011: Add WDT clock and reset entries
  clk: renesas: r9a09g011: Add PFC clock and reset entries
  ...

* clk-spreadtrum:
  clk: sprd: Add dt-bindings include file for UMS512
  dt-bindings: clk: sprd: Add bindings for ums512 clock controller

* clk-imx:
  clk: imx: clk-fracn-gppll: Add more freq config for video pll
  clk: imx: clk-fracn-gppll: correct rdiv
  clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()
  clk: imx: clk-fracn-gppll: fix mfd value
  clk: imx93: Correct the edma1's parent clock
  clk: imx93: correct nic_media parent
  clk: imx93: use adc_root as the parent clock of adc1

* clk-qcom: (62 commits)
  clk: qcom: gcc-msm8994: use parent_hws for gpll0/4
  clk: qcom: clk-rpm: convert to parent_data API
  dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc
  clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies
  clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies
  clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies
  clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions
  clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock
  clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk
  clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled
  clk: qcom: Drop mmcx gdsc supply for dispcc and videocc
  clk: qcom: fix build error initializer element is not constant
  dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources
  clk: qcom: add support for SM8350 DISPCC
  clk: qcom: add support for SM8350 GPUCC
  clk: qcom: add camera clock controller driver for SM8450 SoC
  clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfaces
  clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces
  clk: qcom: clk-alpha-pll: limit exported symbols to GPL licensed code
  clk: qcom: clk-alpha-pll: fix clk_trion_pll_configure description
  ...
2022-08-02 12:20:33 -07:00
Stephen Boyd
f04ed3d9f8 Merge branches 'clk-basic', 'clk-mtk', 'clk-devm-enable' and 'clk-ti-dt' into clk-next
- Remove allwinner workaround logic/compatible in fixed factor code
 - MediaTek clk driver cleanups
 - Add reset support to more MediaTek clk drivers
 - devm helpers for clk_get() + clk_prepare() and clk_enable()

* clk-basic:
  clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()
  clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()
  clk: divider: Introduce devm_clk_hw_register_divider_parent_hw()
  dt-bindings: clock: fixed-factor: Drop Allwinner A10 compatible
  clk: fixed: Remove Allwinner A10 special-case logic

* clk-mtk:
  clk: mediatek: reset: Add infra_ao reset support for MT8186
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8186
  dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186
  clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
  dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195
  clk: mediatek: reset: Add reset support for simple probe
  clk: mediatek: reset: Add new register reset function with device
  clk: mediatek: reset: Change return type for clock reset register function
  clk: mediatek: reset: Support inuput argument index mode
  clk: mediatek: reset: Support nonsequence base offsets of reset registers
  clk: mediatek: reset: Revise structure to control reset register
  clk: mediatek: reset: Merge and revise reset register function
  clk: mediatek: reset: Extract common drivers to update function
  clk: mediatek: reset: Refine and reorder functions in reset.c
  clk: mediatek: reset: Fix written reset bit offset
  clk: mediatek: reset: Add reset.h
  clk: mediatek: Delete MT8192 msdc gate
  dt-bindings: ARM: Mediatek: Remove msdc binding of MT8192 clock

* clk-devm-enable:
  clk: Remove never used devm_clk_*unregister()
  clk: Fix pointer casting to prevent oops in devm_clk_release()
  clk: meson: axg-audio: Don't duplicate devm_clk_get_enabled()
  clk: Provide new devm_clk helpers for prepared and enabled clocks
  clk: generalize devm_clk_get() a bit
  clk: Improve documentation for devm_clk_get() and its optional variant

* clk-ti-dt:
  clk: ti: Stop using legacy clkctrl names for omap4 and 5
2022-08-02 12:19:18 -07:00
Linus Torvalds
47b62edcd4 ARM: SoC drivers for 6.0
The SoC driver updates contain changes to improve support for
 additional SoC variants, as well as cleanups an minor bugfixes
 in a number of existing drivers.
 
 Notable updates this time include:
 
  - Support for Qualcomm MSM8909 (Snapdragon 210) in various drivers
 
  - Updates for interconnect drivers on Qualcomm Snapdragon
 
  - A new driver support for NMI interrupts on Fujitsu A64fx
 
  - A rework of Broadcom BCMBCA Kconfig dependencies
 
  - Improved support for BCM2711 (Raspberry Pi 4) power management
    to allow the use of the V3D GPU
 
  - Cleanups to the NXP guts driver
 
  - Arm SCMI firmware driver updates to add tracing support, and
    use the firmware interfaces for system power control and for
    power capping.
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Merge tag 'arm-drivers-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC drivers from Arnd Bergmann:
 "The SoC driver updates contain changes to improve support for
  additional SoC variants, as well as cleanups an minor bugfixes
  in a number of existing drivers.

  Notable updates this time include:

   - Support for Qualcomm MSM8909 (Snapdragon 210) in various drivers

   - Updates for interconnect drivers on Qualcomm Snapdragon

   - A new driver support for NMI interrupts on Fujitsu A64fx

   - A rework of Broadcom BCMBCA Kconfig dependencies

   - Improved support for BCM2711 (Raspberry Pi 4) power management to
     allow the use of the V3D GPU

   - Cleanups to the NXP guts driver

   - Arm SCMI firmware driver updates to add tracing support, and use
     the firmware interfaces for system power control and for power
     capping"

* tag 'arm-drivers-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (125 commits)
  soc: a64fx-diag: disable modular build
  dt-bindings: soc: qcom: qcom,smd-rpm: add power-controller
  dt-bindings: soc: qcom: aoss: document qcom,sm8450-aoss-qmp
  dt-bindings: soc: qcom,rpmh-rsc: simplify qcom,tcs-config
  ARM: mach-qcom: Add support for MSM8909
  dt-bindings: arm: cpus: Document "qcom,msm8909-smp" enable-method
  soc: qcom: spm: Add CPU data for MSM8909
  dt-bindings: soc: qcom: spm: Add MSM8909 CPU compatible
  soc: qcom: rpmpd: Add compatible for MSM8909
  dt-bindings: power: qcom-rpmpd: Add MSM8909 power domains
  soc: qcom: smd-rpm: Add compatible for MSM8909
  dt-bindings: soc: qcom: smd-rpm: Add MSM8909
  soc: qcom: icc-bwmon: Remove unnecessary print function dev_err()
  soc: fujitsu: Add A64FX diagnostic interrupt driver
  soc: qcom: socinfo: Fix the id of SA8540P SoC
  soc: qcom: Make QCOM_RPMPD depend on PM
  tty: serial: bcm63xx: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  spi: bcm63xx-hsspi: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  clk: bcm: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  hwrng: bcm2835: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  ...
2022-08-02 08:10:10 -07:00
Marijn Suijten
6ebd5247ad clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()
Add the devres and non-devres variant of
clk_hw_register_fixed_factor_parent_hw() for registering a fixed factor
clock with clk_hw parent pointer instead of parent name.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20220629225331.357308-4-marijn.suijten@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-07-29 16:44:08 -07:00
Jernej Skrabec
8dc592c41f clk: sunxi-ng: Fix H6 RTC clock definition
While RTC clock was added in H616 ccu_common list, it was not in H6
list. That caused invalid pointer dereference like this:

Unable to handle kernel NULL pointer dereference at virtual address 000000000000020c
Mem abort info:
  ESR = 0x96000004
  EC = 0x25: DABT (current EL), IL = 32 bits
  SET = 0, FnV = 0
  EA = 0, S1PTW = 0
  FSC = 0x04: level 0 translation fault
Data abort info:
  ISV = 0, ISS = 0x00000004
  CM = 0, WnR = 0
user pgtable: 4k pages, 48-bit VAs, pgdp=000000004d574000
[000000000000020c] pgd=0000000000000000, p4d=0000000000000000
Internal error: Oops: 96000004 [#1] PREEMPT SMP
CPU: 3 PID: 339 Comm: cat Tainted: G    B             5.18.0-rc1+ #1352
Hardware name: Tanix TX6 (DT)
pstate: 00000005 (nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : ccu_gate_is_enabled+0x48/0x74
lr : ccu_gate_is_enabled+0x40/0x74
sp : ffff80000c0b76d0
x29: ffff80000c0b76d0 x28: 00000000016e3600 x27: 0000000000000000
x26: 0000000000000000 x25: 0000000000000002 x24: ffff00000952fe08
x23: ffff800009611400 x22: ffff00000952fe79 x21: 0000000000000000
x20: 0000000000000001 x19: ffff80000aad6f08 x18: 0000000000000000
x17: 2d2d2d2d2d2d2d2d x16: 2d2d2d2d2d2d2d2d x15: 2d2d2d2d2d2d2d2d
x14: 0000000000000000 x13: 00000000f2f2f2f2 x12: ffff700001816e89
x11: 1ffff00001816e88 x10: ffff700001816e88 x9 : dfff800000000000
x8 : ffff80000c0b7447 x7 : 0000000000000001 x6 : ffff700001816e88
x5 : ffff80000c0b7440 x4 : 0000000000000001 x3 : ffff800008935c50
x2 : dfff800000000000 x1 : 0000000000000000 x0 : 000000000000020c
Call trace:
 ccu_gate_is_enabled+0x48/0x74
 clk_core_is_enabled+0x7c/0x1c0
 clk_summary_show_subtree+0x1dc/0x334
 clk_summary_show_subtree+0x250/0x334
 clk_summary_show_subtree+0x250/0x334
 clk_summary_show_subtree+0x250/0x334
 clk_summary_show_subtree+0x250/0x334
 clk_summary_show+0x90/0xdc
 seq_read_iter+0x248/0x6d4
 seq_read+0x17c/0x1fc
 full_proxy_read+0x90/0xf0
 vfs_read+0xdc/0x28c
 ksys_read+0xc8/0x174
 __arm64_sys_read+0x44/0x5c
 invoke_syscall+0x60/0x190
 el0_svc_common.constprop.0+0x7c/0x160
 do_el0_svc+0x38/0xa0
 el0_svc+0x68/0x160
 el0t_64_sync_handler+0x10c/0x140
 el0t_64_sync+0x18c/0x190
Code: d1006260 97e5c981 785e8260 8b0002a0 (b9400000)
---[ end trace 0000000000000000 ]---

Fix that by adding rtc clock to H6 ccu_common list too.

Fixes: 38d321b61b ("clk: sunxi-ng: h6-r: Add RTC gate clock")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220719183725.2605141-1-jernej.skrabec@gmail.com
Reviewed-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-07-27 16:45:58 -07:00
Herve Codina
25c2a075eb clk: lan966x: Fix the lan966x clock gate register address
The register address used for the clock gate register is the base
register address coming from first reg map (ie. the generic
clock registers) instead of the second reg map defining the clock
gate register.

Use the correct clock gate register address.

Fixes: 5ad5915dea ("clk: lan966x: Extend lan966x clock driver for clock gating support")
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20220704102845.168438-2-herve.codina@bootlin.com
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-07-19 00:04:10 -07:00
Dmitry Baryshkov
5e1e12d299 clk: qcom: gcc-msm8994: use parent_hws for gpll0/4
Use parent_hws for two remaining clocks in gcc-msm8994 that used
parent_names.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220620080505.1573948-1-dmitry.baryshkov@linaro.org
2022-07-18 21:40:36 -05:00
Christian Marangi
129d9cd9c2 clk: qcom: clk-rpm: convert to parent_data API
Convert clk-rpm driver to parent_data API.
We keep the old pxo/cxo_board parent naming to keep compatibility with
old DT and we use the new pxo/cxo for new implementation where these
clock are defined in DTS.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706225321.26215-4-ansuelsmth@gmail.com
2022-07-18 19:13:27 -05:00
Bryan O'Donoghue
873b985384 clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies
The shipped qcom driver defines:
static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
        F(  57140000,      gpll0_out_main,  14,    0,    0),
        F(  80000000,      gpll0_out_main,  10,   0,    0),
        F( 100000000,      gpll0_out_main,   8,   0,    0),
        F_END
};
In the upstream code we omit 57.14 MHz and 100 MHz.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220712125922.3461675-7-bryan.odonoghue@linaro.org
2022-07-18 18:55:31 -05:00
Bryan O'Donoghue
2573f7d862 clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies
Again the msm8936/msm8939 supports a wider range of operating frequencies
to the antecedent msm8916 from which the msm8939.c driver is derived.

static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
        F(  50000000,      gpll0_out_aux,  16,    0,    0),
        F(  80000000,      gpll0_out_aux,  10,    0,    0),
        F( 100000000,      gpll0_out_aux,   8,    0,    0),
        F( 145500000,      gpll0_out_aux,  5.5,   0,    0),
        F( 153600000,      gpll1_out_main,      4,      0,      0),
        F( 160000000,      gpll0_out_aux,   5,    0,    0),
        F( 177780000,      gpll0_out_aux, 4.5,    0,    0),
        F( 200000000,      gpll0_out_aux,   4,    0,    0),
        F( 266670000,      gpll0_out_aux,   3,    0,    0),
        F( 307200000,      gpll1_out_main,      2,      0,      0),
        F( 366670000,      gpll3_out_aux,   3,        0,    0),
        F_END
};

We are missing 145.5 MHz and 153.6 MHz.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220712125922.3461675-6-bryan.odonoghue@linaro.org
2022-07-18 18:55:31 -05:00
Bryan O'Donoghue
2c37d70c82 clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies
Reviewing the qcom msm8936.c clock frequency tables we see

static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
        F( 160000000,      gpll0_out_main,   5,   0,    0),
        F( 200000000,      gpll0_out_main,   4,   0,    0),
        F( 228570000,      gpll0_out_main, 3.5,   0,    0),
        F( 266670000,      gpll0_out_main,   3,   0,    0),
        F( 320000000,      gpll0_out_main, 2.5,   0,    0),
        F( 465000000,      gpll2_out_main,   2,   0,    0),
        F_END
};
which is a super-set of the msm8916 original definitions.
Add in the missing frequency definitions now.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220712125922.3461675-5-bryan.odonoghue@linaro.org
2022-07-18 18:55:31 -05:00
Bryan O'Donoghue
680b86da10 clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions
The Venus clock frequencies are a copy/paste error from msm8916. Looking
at the original clock-gcc-8936.c ftbl_gcc_venus0_vcodec0_clk defines we
have:

- 133 MHz
- 200 MHz
- 266 MHz

These values are born out by the relevant qualcomm documentation for the
msm8936/msm8939 Venus core performance levels.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220712125922.3461675-4-bryan.odonoghue@linaro.org
2022-07-18 18:55:31 -05:00
Bryan O'Donoghue
159b2f59d6 clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock
Standard CCI bus clock clocks are 19.2 MHz and 37.5 MHz. We already define
the 19.2 MHz but are missing the 37.5 MHz.

See qcom kernel drivers/clk/qcom/clock-gcc-8936.c::ftbl_gcc_camss_cci_clk[]

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220712125922.3461675-3-bryan.odonoghue@linaro.org
2022-07-18 18:55:31 -05:00
Bryan O'Donoghue
2bc308ebc4 clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk
Adding a new item to this frequency table I see the existing indentation is
incorrect.

Fixes: 1664014e46 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220712125922.3461675-2-bryan.odonoghue@linaro.org
2022-07-18 18:55:31 -05:00
Bjorn Andersson
41fff779d7 clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled
When a GDSC is found to be enabled at boot the pm_runtime state will
be unbalanced as the GDSC is later turned off. Fix this by increasing
the usage counter on the power-domain, in line with how we handled the
regulator state.

Fixes: 1b771839de ("clk: qcom: gdsc: enable optional power domain support")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220713212818.130277-1-bjorn.andersson@linaro.org
2022-07-18 16:35:48 -05:00
Abel Vesa
b1ec8b53c9 clk: qcom: Drop mmcx gdsc supply for dispcc and videocc
Both dispcc and videocc use mmcx power domain now.
Lets drop the supply mmcx from every gdsc.

Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 266e5cf39a ("arm64: dts: qcom: sm8250: remove mmcx regulator")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220713143200.3686765-1-abel.vesa@linaro.org
2022-07-18 16:35:03 -05:00
Ren Zhijie
b5eb8cde86 clk: qcom: fix build error initializer element is not constant
CONFIG_CC_VERSION_TEXT="x86_64-linux-gnu-gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0"
make ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-, will be failed, like this:

drivers/clk/qcom/gpucc-sm8350.c:111:2: error: initializer element is not constant
  gpu_cc_parent,
  ^~~~~~~~~~~~~
drivers/clk/qcom/gpucc-sm8350.c:111:2: note: (near initialization for ‘gpu_cc_parent_data_0[0]’)
drivers/clk/qcom/gpucc-sm8350.c:126:2: error: initializer element is not constant
  gpu_cc_parent,
  ^~~~~~~~~~~~~
drivers/clk/qcom/gpucc-sm8350.c:126:2: note: (near initialization for ‘gpu_cc_parent_data_1[0]’)
make[3]: *** [drivers/clk/qcom/gpucc-sm8350.o] Error 1

It seems that nested constant initializer is not supported in GCC 7.4.0. For portability resons, we should fix it.

Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: 160758b05a ("clk: qcom: add support for SM8350 GPUCC")
Signed-off-by: Ren Zhijie <renzhijie2@huawei.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220714121144.71062-1-renzhijie2@huawei.com
2022-07-16 21:35:55 -05:00
Daniel Latypov
f84a9e9658 clk: explicitly disable CONFIG_UML_PCI_OVER_VIRTIO in .kunitconfig
CONFIG_UML_PCI_OVER_VIRTIO=y is needed to enable CONFIG_PCI=y on UML.
However, this causes test failures when running the clk tests, i.e.
$ ./tools/testing/kunit/kunit.py run --kunitconfig=drivers/clk

A snippet of the particular error is:
>     ok 1 - clk_gate_test_parent_rate
> ------------[ cut here ]------------
> WARNING: CPU: 0 PID: 45 at lib/logic_iomem.c:141 __raw_readl+0x9f/0xd0

This is triggered by this cast in the test:
   143          ctx->fake_mem = (void __force __iomem *)&ctx->fake_reg;
this seems to work except when logic iomem is enabled, i.e.
CONFIG_INDIRECT_IOMEM=y.

As a short-term fix, explicitly disable CONFIG_UML_PCI_OVER_VIRTIO in
drivers/clk/.kunitconfig so we can enable it for everyone else by
default in kunit.py.

The long-term fix probably requires something more complicated, like
  #ifdef CONFIG_INDIRECT_IOMEM
    logic_iomem_add_region(...);
  #endif

Signed-off-by: Daniel Latypov <dlatypov@google.com>
Reported-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: David Gow <davidgow@google.com>
Acked-by: Brendan Higgins <brendanhiggins@google.com>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
2022-07-14 10:35:44 -06:00
William Zhang
45b9fc58ad clk: bcm: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
Prepare for the BCM63138 ARCH_BCM_63XX migration to ARCH_BCMBCA. Make
CLK_BCM_63XX depending and setting default on ARCH_BCMBCA.

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2022-07-10 19:11:16 -07:00
Roman Stratiienko
4167ac8a65 clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS
Using simple bash script it was discovered that not all CCU registers
can be safely used for DFS, e.g.:

    while true
    do
        devmem 0x3001030 4 0xb0003e02
        devmem 0x3001030 4 0xb0001e02
    done

Script above changes the GPU_PLL multiplier register value. While the
script is running, the user should interact with the user interface.

Using this method the following results were obtained:

| Register  | Name           | Bits  | Values | Result |
| --        | --             | --    | --     | --     |
| 0x3001030 | GPU_PLL.MULT   | 15..8 | 20-62  | OK     |
| 0x3001030 | GPU_PLL.INDIV  |     1 | 0-1    | OK     |
| 0x3001030 | GPU_PLL.OUTDIV |     0 | 0-1    | FAIL   |
| 0x3001670 | GPU_CLK.DIV    |  3..0 | ANY    | FAIL   |

DVFS started to work seamlessly once dividers which caused the
glitches were set to fixed values.

Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220705075226.359475-1-r.stratiienko@gmail.com
2022-07-08 18:13:50 +02:00
Jonathan Marek
205737fe33 clk: qcom: add support for SM8350 DISPCC
Add support to the SM8350 display clock controller by extending the SM8250
display clock controller, which is almost identical but has some minor
differences.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-5-robert.foss@linaro.org
2022-07-06 15:20:59 -05:00
Robert Foss
160758b05a clk: qcom: add support for SM8350 GPUCC
The GPUCC manages the clocks for the Adreno GPU found on the
sm8350 SoCs.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706154337.2026269-3-robert.foss@linaro.org
2022-07-06 15:20:59 -05:00
Vladimir Zapolskiy
6082037fe6 clk: qcom: add camera clock controller driver for SM8450 SoC
Add  camera clock controller driver found on Qualcomm SM8450 SoC.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062744.2757931-1-vladimir.zapolskiy@linaro.org
2022-07-06 15:20:59 -05:00
Vladimir Zapolskiy
bbc780132d clk: qcom: clk-alpha-pll: add Rivian EVO PLL configuration interfaces
Add and export Rivian EVO PLL configuration and control functions to
clock controller drivers, the PLL is used by SM8450 camera clock
controller.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062739.2757912-1-vladimir.zapolskiy@linaro.org
2022-07-06 15:20:59 -05:00
Vladimir Zapolskiy
260e36606a clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces
Add controls for Lucid EVO PLL configuration and export control functions
to clock controller drivers, the PLL is used by Qualcomm SM8450 camera
and display clock controllers.

Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062729.2757893-1-vladimir.zapolskiy@linaro.org
2022-07-06 15:20:59 -05:00
Vladimir Zapolskiy
74d40ace3f clk: qcom: clk-alpha-pll: limit exported symbols to GPL licensed code
Unify all exported PLL clock configuration functions and data structures
as GPL symbols.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062720.2757874-1-vladimir.zapolskiy@linaro.org
2022-07-06 15:20:58 -05:00
Vladimir Zapolskiy
94bed9bb05 clk: qcom: clk-alpha-pll: fix clk_trion_pll_configure description
After merging lucid and trion pll functions in commit 0b01489475
("clk: qcom: clk-alpha-pll: same regs and ops for trion and lucid")
the function clk_trion_pll_configure() is left with an old description
header, which results in a W=2 compile time warning, fix it.

Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220701062711.2757855-1-vladimir.zapolskiy@linaro.org
2022-07-06 15:20:58 -05:00
Andi Kleen
0e704f6c42 clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config
A variable pointing to const isn't const itself. It'd have to contain
"const" keyword after "*" too. Therefore, cpg_pll_config cannot be put
to "rodata".  Hence use __initdata instead of __initconst to fix this.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
[js] more explanatory commit message.
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220623083217.26433-2-jslaby@suse.cz
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:20:34 +02:00
Lad Prabhakar
95d48d2703 clk: renesas: r9a07g043: Add support for RZ/Five SoC
Renesas RZ/Five SoC has almost the same clock structure compared to the
Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.c file to add support for
RZ/Five SoC.

This patch splits up the clocks and reset arrays for RZ/G2UL and RZ/Five
SoC using #ifdef CONFIG_ARM64 and #ifdef CONFIG_RISCV checks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220622181723.13033-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-07-05 09:20:34 +02:00
Dmitry Baryshkov
93b793d88d clk: qcom: gcc-msm8960: create tsens device if there are no child nodes
Currently gcc-msm8960 driver manually creates tsens platform device
manually. It would be better to follow IPQ8064 approach, where tsens
device is defined as gcc's child device in the device tree. If nothing
else, it removes gcc's dependency on QFPROM, thus allowing clock
controller to be probed earlier.

Don't create it in case there are available child nodes (tsens) inside
the gcc's device tree node.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220521151437.1489111-4-dmitry.baryshkov@linaro.org
2022-07-04 21:58:39 -05:00
Samuel Holland
b17403a560 clk: sunxi: Do not select the PRCM MFD
The PRCM MFD driver is already selected by the two platforms where it is
actually used (MACH_SUN6I and MACH_SUN8I). Selecting it here builds it
unnecessarily on the rest of the Allwinner platforms.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220702190135.51744-2-samuel@sholland.org
2022-07-04 21:59:30 +02:00
Samuel Holland
2b4c206963 clk: sunxi: Limit legacy clocks to 32-bit ARM
The sunxi legacy clocks were never compatible with any 64-bit SoC,
so there is no point in building them as part of a 64-bit ARM kernel.
They make even less sense being built in to a 64-bit RISC-V kernel.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220702190135.51744-1-samuel@sholland.org
2022-07-04 21:59:19 +02:00
Nikita Travkin
bf8bb8eacc clk: qcom: gcc-msm8916: Add rates to the GP clocks
msm8916 has (at least) 6 "General Purpose" clocks that can be muxed to
SoC pins. These clocks are:

GP_CLK{0, 1} : GPIO_{31, 32} (Belongs to CAMSS according to Linux)
GP_CLK_{1-3}{A, B} : GPIO_{49-51, 97, 12, 13} (Belongs to GCC itself)
GP_MN : GPIO_110 (Doesn't seem to be described in gcc,
    ignored in this patch)

Those clocks may be used as e.g. PWM sources for external peripherals.
Add more frequencies to the table for those clocks so it's possible
for arbitrary peripherals to make use of them.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220612145955.385787-5-nikita@trvn.ru
2022-06-30 22:34:13 -05:00
Nikita Travkin
d0696770ce clk: qcom: clk-rcg2: Make sure to not write d=0 to the NMD register
Sometimes calculation of d value may result in 0 because of the
rounding after integer division. This causes the following error:

[  113.969689] camss_gp1_clk_src: rcg didn't update its configuration.
[  113.969754] WARNING: CPU: 3 PID: 35 at drivers/clk/qcom/clk-rcg2.c:122 update_config+0xc8/0xdc

Make sure that D value is never zero.

Fixes: 7f891faf59 ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG")
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220612145955.385787-3-nikita@trvn.ru
2022-06-30 22:34:13 -05:00
Nikita Travkin
bdafb609c3 clk: qcom: clk-rcg2: Fail Duty-Cycle configuration if MND divider is not enabled.
In cases when MND is not enabled (e.g. when only Half Integer Divider is
used), setting D registers makes no effect.

Fail instead of making ineffective write.

Fixes: 7f891faf59 ("clk: qcom: clk-rcg2: Add support for duty-cycle for RCG")
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220612145955.385787-2-nikita@trvn.ru
2022-06-30 22:34:13 -05:00
Vladimir Zapolskiy
f8acf01a6a clk: qcom: camcc-sm8250: Fix topology around titan_top power domain
On SM8250 two found VFE GDSC power domains shall not be operated, if
titan top is turned off, thus the former power domains will be set as
subdomains by a GDSC registration routine.

Fixes: 5d66ca79b5 ("clk: qcom: Add camera clock controller driver for SM8250")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220519214133.1728979-3-vladimir.zapolskiy@linaro.org
2022-06-30 18:34:55 -05:00
Vladimir Zapolskiy
103dd2338b clk: qcom: camcc-sdm845: Fix topology around titan_top power domain
On SDM845 two found VFE GDSC power domains shall not be operated, if
titan top is turned off, thus the former power domains will be set as
subdomains by a GDSC registration routine.

Fixes: 78412c2620 ("clk: qcom: Add camera clock controller driver for SDM845")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220519214133.1728979-2-vladimir.zapolskiy@linaro.org
2022-06-30 18:34:54 -05:00
Robert Marko
1bf7305e79 clk: qcom: ipq8074: dont disable gcc_sleep_clk_src
Once the usb sleep clocks are disabled, clock framework is trying to
disable the sleep clock source also.

However, it seems that it cannot be disabled and trying to do so produces:
[  245.436390] ------------[ cut here ]------------
[  245.441233] gcc_sleep_clk_src status stuck at 'on'
[  245.441254] WARNING: CPU: 2 PID: 223 at clk_branch_wait+0x130/0x140
[  245.450435] Modules linked in: xhci_plat_hcd xhci_hcd dwc3 dwc3_qcom leds_gpio
[  245.456601] CPU: 2 PID: 223 Comm: sh Not tainted 5.18.0-rc4 #215
[  245.463889] Hardware name: Xiaomi AX9000 (DT)
[  245.470050] pstate: 204000c5 (nzCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[  245.474307] pc : clk_branch_wait+0x130/0x140
[  245.481073] lr : clk_branch_wait+0x130/0x140
[  245.485588] sp : ffffffc009f2bad0
[  245.489838] x29: ffffffc009f2bad0 x28: ffffff8003e6c800 x27: 0000000000000000
[  245.493057] x26: 0000000000000000 x25: 0000000000000000 x24: ffffff800226ef20
[  245.500175] x23: ffffffc0089ff550 x22: 0000000000000000 x21: ffffffc008476ad0
[  245.507294] x20: 0000000000000000 x19: ffffffc00965ac70 x18: fffffffffffc51a7
[  245.514413] x17: 68702e3030303837 x16: 3a6d726f6674616c x15: ffffffc089f2b777
[  245.521531] x14: ffffffc0095c9d18 x13: 0000000000000129 x12: 0000000000000129
[  245.528649] x11: 00000000ffffffea x10: ffffffc009621d18 x9 : 0000000000000001
[  245.535767] x8 : 0000000000000001 x7 : 0000000000017fe8 x6 : 0000000000000001
[  245.542885] x5 : ffffff803fdca6d8 x4 : 0000000000000000 x3 : 0000000000000027
[  245.550002] x2 : 0000000000000027 x1 : 0000000000000023 x0 : 0000000000000026
[  245.557122] Call trace:
[  245.564229]  clk_branch_wait+0x130/0x140
[  245.566490]  clk_branch2_disable+0x2c/0x40
[  245.570656]  clk_core_disable+0x60/0xb0
[  245.574561]  clk_core_disable+0x68/0xb0
[  245.578293]  clk_disable+0x30/0x50
[  245.582113]  dwc3_qcom_remove+0x60/0xc0 [dwc3_qcom]
[  245.585588]  platform_remove+0x28/0x60
[  245.590361]  device_remove+0x4c/0x80
[  245.594179]  device_release_driver_internal+0x1dc/0x230
[  245.597914]  device_driver_detach+0x18/0x30
[  245.602861]  unbind_store+0xec/0x110
[  245.607027]  drv_attr_store+0x24/0x40
[  245.610847]  sysfs_kf_write+0x44/0x60
[  245.614405]  kernfs_fop_write_iter+0x128/0x1c0
[  245.618052]  new_sync_write+0xc0/0x130
[  245.622391]  vfs_write+0x1d4/0x2a0
[  245.626123]  ksys_write+0x58/0xe0
[  245.629508]  __arm64_sys_write+0x1c/0x30
[  245.632895]  invoke_syscall.constprop.0+0x5c/0x110
[  245.636890]  do_el0_svc+0xa0/0x150
[  245.641488]  el0_svc+0x18/0x60
[  245.644872]  el0t_64_sync_handler+0xa4/0x130
[  245.647914]  el0t_64_sync+0x174/0x178
[  245.652340] ---[ end trace 0000000000000000 ]---

So, add CLK_IS_CRITICAL flag to the clock so that the kernel won't try
to disable the sleep clock.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-10-robimarko@gmail.com
2022-06-30 18:24:54 -05:00
Robert Marko
8add990ace clk: qcom: ipq8074: add USB GDSCs
Add GDSC-s for each of the two USB controllers built-in the IPQ8074.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com
2022-06-30 18:24:54 -05:00
Robert Marko
2bd357e698 clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks
Currently, attempting to enable the UBI clocks will cause the stuck at
off warning to be printed and clk_enable will fail.

[   14.936694] gcc_ubi1_ahb_clk status stuck at 'off'

Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY
flag on UBI clocks, so lets do the same.

Fixes: 5736294aef ("clk: qcom: ipq8074: add NSS clocks")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-6-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Robert Marko
74521205b6 clk: qcom: ipq8074: add PPE crypto clock
The built-in PPE engine has a dedicated clock for the EIP-197 crypto
engine.

So, since the required clock currently missing add support for it.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Robert Marko
0e9e61a281 clk: qcom: ipq8074: fix NSS port frequency tables
NSS port 5 and 6 frequency tables are currently broken and are causing a
wide ranges of issue like 1G not working at all on port 6 or port 5 being
clocked with 312 instead of 125 MHz as UNIPHY1 gets selected.

So, update the frequency tables with the ones from the downstream QCA 5.4
based kernel which has already fixed this.

Fixes: 7117a51ed3 ("clk: qcom: ipq8074: add NSS ethernet port clocks")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-3-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Robert Marko
3401ea2856 clk: qcom: ipq8074: SW workaround for UBI32 PLL lock
UBI32 Huayra PLL fails to lock in 5 us in some SoC silicon and thus it
will cause the wait_for_pll() to timeout and thus return the error
indicating that the PLL failed to lock.

This is bug in Huayra PLL HW for which SW workaround
is to set bit 26 of TEST_CTL register.

This is ported from the QCA 5.4 based downstream kernel.

Fixes: b8e7e51962 ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-2-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Robert Marko
ca41ec1b30 clk: qcom: ipq8074: fix NSS core PLL-s
Like in IPQ6018 the NSS related Alpha PLL-s require initial configuration
to work.

So, obtain the regmap that is required for the Alpha PLL configuration
and thus utilize the qcom_cc_really_probe() as we already have the regmap.
Then utilize the Alpha PLL configs from the downstream QCA 5.4 based
kernel to configure them.

This fixes the UBI32 and NSS crypto PLL-s failing to get enabled by the
kernel.

Fixes: b8e7e51962 ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-1-robimarko@gmail.com
2022-06-30 18:06:13 -05:00
Bryan O'Donoghue
05eed09909 clk: qcom: gcc-msm8939: Point MM peripherals to system_mm_noc clock
Qcom docs indciate the following peripherals operating from System NOC
MM not from System NOC clocks.

- MDP
- VFE
- JPEGe
- Venus

Switch over the relevant parent pointers.

Fixes: 1664014e46 ("clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220504163835.40130-5-bryan.odonoghue@linaro.org
2022-06-29 22:47:38 -05:00