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Author SHA1 Message Date
Stephen Boyd
a1ff1ce300 Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' into clk-next 
- Set clk_init_data pointer inside clk_hw to NULL after registration

* clk-init-destroy:
  clk: Overwrite clk_hw::init with NULL during clk_register()
  clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered
  clk: ti: Don't reference clk_init_data after registration
  clk: qcom: Remove error prints from DFS registration
  rtc: sun6i: Don't reference clk_init_data after registration
  clk: zx296718: Don't reference clk_init_data after registration
  clk: milbeaut: Don't reference clk_init_data after registration
  clk: socfpga: deindent code to proper indentation
  phy: ti: am654-serdes: Don't reference clk_init_data after registration
  clk: sprd: Don't reference clk_init_data after registration
  clk: socfpga: Don't reference clk_init_data after registration
  clk: sirf: Don't reference clk_init_data after registration
  clk: qcom: Don't reference clk_init_data after registration
  clk: meson: axg-audio: Don't reference clk_init_data after registration
  clk: lochnagar: Don't reference clk_init_data after registration
  clk: actions: Don't reference clk_init_data after registration

* clk-doc:
  clk: remove extra ---help--- tags in Kconfig
  clk: add include guard to clk-conf.h
  clk: Document of_parse_clkspec() some more
  clk: Remove extraneous 'for' word in comments

* clk-imx: (32 commits)
  clk: imx: imx8mn: fix pll mux bit
  clk: imx: imx8mm: fix pll mux bit
  clk: imx: clk-pll14xx: unbypass PLL by default
  clk: imx: pll14xx: avoid glitch when set rate
  clk: imx: imx8mn: fix audio pll setting
  clk: imx8mn: Add necessary frequency support for ARM PLL table
  clk: imx8mn: Add missing rate_count assignment for each PLL structure
  clk: imx8mn: fix int pll clk gate
  clk: imx8mn: Add GIC clock
  clk: imx8mn: Fix incorrect parents
  clk: imx8mm: Fix incorrect parents
  clk: imx8mq: Fix sys3 pll references
  clk: imx8mq: Unregister clks when of_clk_add_provider failed
  clk: imx8mm: Unregister clks when of_clk_add_provider failed
  clk: imx8mq: Mark AHB clock as critical
  clk: imx8mn: Keep uart clocks on for early console
  clk: imx: Remove unused function statement
  clk: imx7ulp: Make sure earlycon's clock is enabled
  clk: imx8mm: Switch to platform driver
  clk: imx: imx8mm: fix audio pll setting
  ...

* clk-allwinner:
  clk: sunxi-ng: h6: Allow I2S to change parent rate
  clk: sunxi-ng: v3s: add Allwinner V3 support
  clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
  dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
  clk: sunxi-ng: v3s: add the missing PLL_DDR1
 2019-09-19 15:31:27 -07:00
Stephen Boyd
f5c7305db3 Merge branches 'clk-qcom', 'clk-mtk', 'clk-armada', 'clk-ingenic' and 'clk-meson' into clk-next 
- Support qcom SM8150 RPMh clks
 - Set floor ops for qcom sd clks
 - Support qcom QCS404 WCSS clks
 - Support for Mediatek MT6779 SoCs
 - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)

* clk-qcom:
  clk: qcom: rcg: Return failure for RCG update
  clk: qcom: fix QCS404 TuringCC regmap
  clk: qcom: clk-rpmh: Add support for SM8150
  dt-bindings: clock: Document SM8150 rpmh-clock compatible
  clk: qcom: clk-rpmh: Convert to parent data scheme
  dt-bindings: clock: Document the parent clocks
  clk: qcom: gcc: Use floor ops for SDCC clocks
  clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
  clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
  clk: qcom: define probe by index API as common API
  clk: qcom: Add WCSS gcc clock control for QCS404
  clk: qcom: msm8916: Don't build by default
  clk: qcom: gcc: Add global clock controller driver for SM8150
  dt-bindings: clock: Document gcc bindings for SM8150
  clk: qcom: clk-alpha-pll: Add support for Trion PLLs
  clk: qcom: clk-alpha-pll: Remove post_div_table checks
  clk: qcom: clk-alpha-pll: Remove unnecessary cast

* clk-mtk:
  clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
  clk: mediatek: Register clock gate with device
  clk: mediatek: add pericfg clocks for MT8183
  dt-bindings: clock: mediatek: add pericfg for MT8183
  clk: mediatek: Add MT6779 clock support
  clk: mediatek: Add dt-bindings for MT6779 clocks
  dt-bindings: mediatek: bindings for MT6779 clk
  clk: reset: Modify reset-controller driver

* clk-armada:
  clk: mvebu: ap80x: add AP807 clock support
  clk: mvebu: ap806: Prepare the introduction of AP807 clock support
  clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
  clk: mvebu: ap806: be more explicit on what SaR is
  clk: mvebu: ap80x-cpu: add AP807 CPU clock support
  clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
  dt-bindings: ap806: Document AP807 clock compatible
  dt-bindings: ap80x: Document AP807 CPU clock compatible
  clk: mvebu: ap806: Fix clock name for the cluster
  clk: mvebu: add CPU clock driver for Armada 7K/8K
  clk: mvebu: add helper file for Armada AP and CP clocks
  dt-bindings: ap806: add the cluster clock node in the syscon file

* clk-ingenic:
  clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro
  clk: ingenic/jz4740: Fix "pll half" divider not read/written properly

* clk-meson: (23 commits)
  clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
  clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
  clk: meson: g12a: add support for SM1 GP1 PLL
  dt-bindings: clk: meson: add sm1 periph clock controller bindings
  clk: meson: axg-audio: add g12a reset support
  dt-bindings: clock: meson: add resets to the audio clock controller
  clk: meson: g12a: expose CPUB clock ID for G12B
  clk: meson: g12a: add notifiers to handle cpu clock change
  clk: meson: add g12a cpu dynamic divider driver
  clk: core: introduce clk_hw_set_parent()
  clk: meson: remove clk input helper
  clk: meson: remove ee input bypass clocks
  clk: meson: clk-regmap: migrate to new parent description method
  clk: meson: meson8b: migrate to the new parent description method
  clk: meson: axg: migrate to the new parent description method
  clk: meson: gxbb: migrate to the new parent description method
  clk: meson: g12a: migrate to the new parent description method
  clk: meson: remove ao input bypass clocks
  clk: meson: axg-aoclk: migrate to the new parent description method
  clk: meson: gxbb-aoclk: migrate to the new parent description method
  ...
 2019-09-19 15:30:59 -07:00
Stephen Boyd
cee99529ee Merge branches 'clk-aspeed', 'clk-unused', 'clk-of-node-put', 'clk-const-bulk-data' and 'clk-debugfs' into clk-next 
- Add SDIO gate to aspeed driver
 - Support aspeed AST2600 SoC
 - Add missing of_node_put() calls in various clk drivers
 - Drop NULL checks in clk debugfs
 - Add min/max rates to clk debugfs

* clk-aspeed:
  clk: Add support for AST2600 SoC
  clk: aspeed: Move structures to header
  clk: aspeed: Add SDIO gate

* clk-unused:
  clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'
  clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'
  clk: composite: Drop unused clk.h include
  clk: Si5341/Si5340: remove redundant assignment to n_den
  clk: qoriq: Fix -Wunused-const-variable

* clk-of-node-put:
  clk: ti: dm814x: Add of_node_put() to prevent memory leak
  clk: st: clk-flexgen: Add of_node_put() in st_of_flexgen_setup()
  clk: davinci: pll: Add of_node_put() in of_davinci_pll_init()
  clk: versatile: Add of_node_put() in cm_osc_setup()

* clk-const-bulk-data:
  clk: Constify struct clk_bulk_data * where possible

* clk-debugfs:
  clk: Drop !clk checks in debugfs dumping
  clk: Use seq_puts() in possible_parent_show()
  clk: Assert prepare_lock in clk_core_get_boundaries
  clk: Add clk_min/max_rate entries in debugfs
 2019-09-19 15:30:40 -07:00
Stephen Boyd
7f4804665b clk: Drop !clk checks in debugfs dumping 
These recursive functions have checks for !clk being passed in, but the
callers are always looping through lists and therefore the pointers
can't be NULL. Drop the checks to simplify the code.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190826234729.145593-1-sboyd@kernel.org
 2019-09-19 15:26:36 -07:00
Peng Fan
60a8a148b2 clk: imx: imx8mn: fix pll mux bit 
pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.

So use EXT_BYPASS bit here.

And drop uneeded set parent, because EXT_BYPASS default is 0.

Suggested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-5-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:53:34 -07:00
Peng Fan
67315be33e clk: imx: imx8mm: fix pll mux bit 
pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.

So use EXT_BYPASS bit here.

And drop uneeded set parent, because EXT_BYPASS default is 0.

Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Suggested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-4-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:53:34 -07:00
Peng Fan
a9aa830607 clk: imx: clk-pll14xx: unbypass PLL by default 
When registering the PLL, unbypass the PLL.
The PLL has two bypass control bit, BYPASS and EXT_BYPASS.
we will expose EXT_BYPASS to clk driver for mux usage, and keep
BYPASS inside pll14xx usage. The PLL has a restriction that
when M/P change, need to RESET/BYPASS pll to avoid glitch, so
we could not expose BYPASS.

To make it easy for clk driver usage, unbypass PLL which does
not hurt current function.

Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-3-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:53:34 -07:00
Peng Fan
dee1bc9c23 clk: imx: pll14xx: avoid glitch when set rate 
According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."

So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
In the end of set rate, BYPASS will be cleared.

When prepare clock, also need to take care to avoid glitch. So
we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
And add a check if the RESETB is already 0, directly return 0;

Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-2-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:53:34 -07:00
Ben Peled
c0448dce56 clk: mvebu: ap80x: add AP807 clock support 
Add driver support for AP807 clock.

Signed-off-by: Ben Peled <bpeled@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-9-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:15:41 -07:00
Ben Peled
be69e55df9 clk: mvebu: ap806: Prepare the introduction of AP807 clock support 
Factor out the code that is only useful to AP806 so it will be easier
to support AP807. No functional changes.

Signed-off-by: Ben Peled <bpeled@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-8-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:15:41 -07:00
Omri Itach
0099dc446b clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver 
Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK
is half the rate of DDR clock, so its derrived from Sample At Reset
configuration. The clock frequency is required for AP806 AXI monitor
profiling feature.

Signed-off-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-7-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:15:41 -07:00
Miquel Raynal
cd016cb018 clk: mvebu: ap806: be more explicit on what SaR is 
"SaR" means Sample at Reset. DIP switches can be changed on the board,
their states at reset time is available through a register read.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-6-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:15:41 -07:00
Ben Peled
3b14e509ab clk: mvebu: ap80x-cpu: add AP807 CPU clock support 
Enhance the ap-cpu-clk driver to support both AP806 and AP807 CPU
clocks.

Signed-off-by: Ben Peled <bpeled@marvell.com>
[<miquel.raynal@bootlin.com>: use device data instead of conditions on
the compatible]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-5-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:15:40 -07:00
Christine Gharzuzi
a77f45eaa2 clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock 
This patch allows same flow to be executed on chips with different
register mappings like AP806 and, in the future, AP807.

Note: this patch has no functional effect, and only prepares the
driver for additional chips to be supported by retrieving the right
device data depenging on the compatible property.

Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-4-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:15:40 -07:00
Miquel Raynal
64b379543e dt-bindings: ap806: Document AP807 clock compatible 
Add AP807 clock compatible to the bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-3-miquel.raynal@bootlin.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:15:40 -07:00
Miquel Raynal
d827af8f37 dt-bindings: ap80x: Document AP807 CPU clock compatible 
Add AP807 CPU clock compatible to the bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-2-miquel.raynal@bootlin.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:15:40 -07:00
Taniya Das
21ea4b62e1 clk: qcom: rcg: Return failure for RCG update 
In case of update config failure, return -EBUSY, so that consumers could
handle the failure gracefully.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1557339895-21952-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 10:29:39 -07:00
Lubomir Rintel
863e53e6ed clk: remove extra ---help--- tags in Kconfig 
Sometimes an extraneous "---help---" follows "help". That is probably a
copy&paste error stemming from their inconsistent use. Remove those.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20190822093126.594013-1-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 10:27:57 -07:00
Masahiro Yamada
d7aef6ef96 clk: add include guard to clk-conf.h 
Add a header include guard just in case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lkml.kernel.org/r/20190820030536.1181-1-yamada.masahiro@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 10:27:46 -07:00
Weiyi Lu
327aa74156 clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider 
Enable the runtime PM support and forward the struct device pointer for
registration of MT8183 mcucfg clocks.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-3-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 10:22:49 -07:00
Weiyi Lu
e4c23e19aa clk: mediatek: Register clock gate with device 
Allow those clocks under a power domain to do the runtime pm operation
by forwarding the struct device pointer from clock provider.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-2-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 10:22:49 -07:00
Chunfeng Yun
f9e55ac22c clk: mediatek: add pericfg clocks for MT8183 
Add pericfg clocks for MT8183, it's used when support USB
remote wakeup

Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lkml.kernel.org/r/1566980533-28282-2-git-send-email-chunfeng.yun@mediatek.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 10:17:41 -07:00
Chunfeng Yun
5aa00ad3fd dt-bindings: clock: mediatek: add pericfg for MT8183 
This patch adds binding of pericfg for MT8183.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lkml.kernel.org/r/1566980533-28282-1-git-send-email-chunfeng.yun@mediatek.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 10:17:39 -07:00
mtk01761
710774e048 clk: mediatek: Add MT6779 clock support 
Add MT6779 clock support, include topckgen, apmixedsys,
infracfg, and subsystem clocks.

Signed-off-by: mtk01761 <wendell.lin@mediatek.com>
Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 09:37:30 -07:00
mtk01761
85b18fe704 clk: mediatek: Add dt-bindings for MT6779 clocks 
Add MT6779 clock dt-bindings, include topckgen, apmixedsys,
infracfg, and subsystem clocks.

Signed-off-by: mtk01761 <wendell.lin@mediatek.com>
Link: https://lkml.kernel.org/r/1566206502-4347-10-git-send-email-mars.cheng@mediatek.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 09:37:29 -07:00
mtk01761
171f68a3b2 dt-bindings: mediatek: bindings for MT6779 clk 
This patch adds the binding documentation for
apmixedsys, audiosys, camsys, imgsys, ipesys,
infracfg, mfgcfg, mmsys, topckgen, vdecsys,
and vencsys for Mediatek MT6779.

Signed-off-by: mtk01761 <wendell.lin@mediatek.com>
Link: https://lkml.kernel.org/r/1566206502-4347-9-git-send-email-mars.cheng@mediatek.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 09:37:29 -07:00
Jorge Ramirez-Ortiz
3bcff3e45b clk: qcom: fix QCS404 TuringCC regmap 
The max register is 0x23004 as per the manual (the current
max_register that this commit is fixing is actually out of bounds).

Fixes: 892df0191b29 ("clk: qcom: Add QCS404 TuringCC")
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Link: https://lkml.kernel.org/r/20190909085430.8700-1-jorge.ramirez-ortiz@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 09:05:22 -07:00
Vinod Koul
2243fd4186 clk: qcom: clk-rpmh: Add support for SM8150 
Add support for rpmh clocks found in SM8150

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-5-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 04:40:10 -07:00
Vinod Koul
51ffc35d68 dt-bindings: clock: Document SM8150 rpmh-clock compatible 
Document the SM8150 rpmh-clock compatible for rpmh clock controller
found on SM8150 platforms.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-4-vkoul@kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 04:40:10 -07:00
Vinod Koul
a64a9e5172 clk: qcom: clk-rpmh: Convert to parent data scheme 
Convert the rpmh clock driver to use the new parent data scheme by
specifying the parent data for board clock.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-3-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 04:40:10 -07:00
Vinod Koul
8c758d6675 dt-bindings: clock: Document the parent clocks 
With clock parent data scheme we must specify the parent clocks for the
rpmhcc nodes. So describe the parent clock for rpmhcc in the bindings.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-2-vkoul@kernel.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 04:40:10 -07:00
Taniya Das
3f905469c8 clk: qcom: gcc: Use floor ops for SDCC clocks 
Update global clock controller SDCC2/4 clocks to use the floor rcg ops,
so as to use the rounded down clock rates for these clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20190909074410.18977-1-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 04:39:12 -07:00
Vinod Koul
593020811c clk: qcom: gcc-qcs404: Use floor ops for sdcc clks 
Update the gcc qcs404 clock driver to use floor ops for sdcc clocks. As
disuccsed in [1] it is good idea to use floor ops for sdcc clocks as we
dont want the clock rates to do round up.

[1]: https://lore.kernel.org/linux-arm-msm/20190830195142.103564-1-swboyd@chromium.org/

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190906045659.20621-1-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 04:38:22 -07:00
Stephen Boyd
5e4b7e82d4 clk: qcom: gcc-sdm845: Use floor ops for sdcc clks 
Some MMC cards fail to enumerate properly when inserted into an MMC slot
on sdm845 devices. This is because the clk ops for qcom clks round the
frequency up to the nearest rate instead of down to the nearest rate.
For example, the MMC driver requests a frequency of 52MHz from
clk_set_rate() but the qcom implementation for these clks rounds 52MHz
up to the next supported frequency of 100MHz. The MMC driver could be
modified to request clk rate ranges but for now we can fix this in the
clk driver by changing the rounding policy for this clk to be round down
instead of round up.

Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Reported-by: Douglas Anderson <dianders@chromium.org>
Cc: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lkml.kernel.org/r/20190830195142.103564-1-swboyd@chromium.org
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-09 04:38:20 -07:00
Joel Stanley
d3d04f6c33 clk: Add support for AST2600 SoC 
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks
than the previous iterations, so support is broken out into it's own
driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20190825141848.17346-3-joel@jms.id.au
[sboyd@kernel.org: Mark arrays const]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-06 15:22:29 -07:00
Joel Stanley
c1c4942eeb clk: aspeed: Move structures to header 
They will be reused by the ast2600 driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20190825141848.17346-2-joel@jms.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-06 15:17:02 -07:00
YueHaibing
8863a5bf68 clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0' 
drivers/clk/st/clkgen-pll.c:64:37: warning:
 st_pll3200c32_407_a0 defined but not used [-Wunused-const-variable=]

It is never used, so can be removed.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20190816135523.73520-1-yuehaibing@huawei.com
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-06 10:26:58 -07:00
YueHaibing
e03a47deaf clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops' 
drivers/clk/st/clkgen-fsyn.c:70:29: warning:
 st_quadfs_fs660c32_ops defined but not used [-Wunused-const-variable=]

It is never used, so can be removed.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20190816135341.52248-1-yuehaibing@huawei.com
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-06 10:26:32 -07:00
Stephen Boyd
226fd70209 clk: Document of_parse_clkspec() some more 
The return value of of_parse_clkspec() is peculiar. If the function is
called with a NULL argument for 'name' it will return -ENOENT, but if
it's called with a non-NULL argument for 'name' it will return -EINVAL.
This peculiarity is documented by commit 5c56dfe63b6e ("clk: Add comment
about __of_clk_get_by_name() error values").

Let's further document this function so that it's clear what the return
value is and how to use the arguments to parse clk specifiers.

Cc: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190826212042.48642-1-sboyd@kernel.org
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
 2019-09-05 11:51:31 -07:00
Stephen Boyd
924a8c6eda Allwinner clock changes for 5.4 
A few patches to enable the V3 SoC and fix the i2s clock for the H6.
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Merge tag 'sunxi-clk-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

A few patches to enable the V3 SoC and fix the i2s clock for the H6.

* tag 'sunxi-clk-for-5.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: h6: Allow I2S to change parent rate
  clk: sunxi-ng: v3s: add Allwinner V3 support
  clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
  dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
  clk: sunxi-ng: v3s: add the missing PLL_DDR1
 2019-09-04 11:14:51 -07:00
Stephen Boyd
9ea67d14a8 i.MX clock changes for 5.4: 
- Add clock driver for i.MX8MN SoC.
  - Switch i.MX8MM clock driver to platform driver.
  - Add API for clk unregister when driver probe fail.
  - Add Hifi4 DSP related clocks for i.MX8QXP SoC.
  - Fix Audio PLL setting and parent clock for USB.
  - Misc i.MX8 clock driver improvements and corrections.
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Merge tag 'clk-imx-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-imx

Pull i.MX clock changes from Shawn Guo:

 - Add clock driver for i.MX8MN SoC
 - Switch i.MX8MM clock driver to platform driver
 - Add API for clk unregister when driver probe fail
 - Add Hifi4 DSP related clocks for i.MX8QXP SoC
 - Fix Audio PLL setting and parent clock for USB
 - Misc i.MX8 clock driver improvements and corrections

* tag 'clk-imx-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (28 commits)
  clk: imx: imx8mn: fix audio pll setting
  clk: imx8mn: Add necessary frequency support for ARM PLL table
  clk: imx8mn: Add missing rate_count assignment for each PLL structure
  clk: imx8mn: fix int pll clk gate
  clk: imx8mn: Add GIC clock
  clk: imx8mn: Fix incorrect parents
  clk: imx8mm: Fix incorrect parents
  clk: imx8mq: Fix sys3 pll references
  clk: imx8mq: Unregister clks when of_clk_add_provider failed
  clk: imx8mm: Unregister clks when of_clk_add_provider failed
  clk: imx8mq: Mark AHB clock as critical
  clk: imx8mn: Keep uart clocks on for early console
  clk: imx: Remove unused function statement
  clk: imx7ulp: Make sure earlycon's clock is enabled
  clk: imx8mm: Switch to platform driver
  clk: imx: imx8mm: fix audio pll setting
  clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m
  clk: imx8mm: Fix typo of pwm3 clock's mux option #4
  clk: imx: Remove unused clk based API
  clk: imx8mq: set correct parent for usb ctrl clocks
  ...
 2019-09-04 11:00:15 -07:00
Stephen Boyd
5a85a64257 Amlogic 2nd round of clock changes for v5.4 
* Add g12a reset support to the axg audio clock controller
 * Add sm1 support to the g12a clock controller
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Merge tag 'clk-meson-v5.4-2' of https://github.com/BayLibre/clk-meson into clk-meson

Pull second set of Amlogic clk driver updates from Jerome Brunet:

 - Add g12a reset support to the axg audio clock controller
 - Add sm1 support to the g12a clock controller

* tag 'clk-meson-v5.4-2' of https://github.com/BayLibre/clk-meson:
  clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
  clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
  clk: meson: g12a: add support for SM1 GP1 PLL
  dt-bindings: clk: meson: add sm1 periph clock controller bindings
  clk: meson: axg-audio: add g12a reset support
  dt-bindings: clock: meson: add resets to the audio clock controller
 2019-09-04 10:53:34 -07:00
Neil Armstrong
da3ceae4ec clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks 
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.

But since the cluster only has a single power rail and shares a single PLL,
it's not worth adding 3 unsused clock tree, so we add only the mux to
select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores.

They are set read-only because the early boot stages sets them to select
the CPU0 input clock.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2019-08-26 11:04:54 +02:00
Neil Armstrong
2edccd319f clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock 
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to
the CPU clock tree with a supplementaty mux to select the CPU0 clock
instead.

Leave this as read-only since it's set up by the early boot stages.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2019-08-26 11:04:42 +02:00
Neil Armstrong
3dd02b7334 clk: meson: g12a: add support for SM1 GP1 PLL 
Add the new GP1 PLL for the Amlogic SM1 SoC, used to feed the new
DynamIQ Shared Unit of the ARM Cores Complex.

This also adds a dedicated set of clock and compatible for SM1.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2019-08-26 11:03:38 +02:00
Jerome Brunet
1db61d5eda Merge branch 'v5.4/dt' into v5.4/drivers 2019-08-26 11:01:20 +02:00
Neil Armstrong
cda4569137 dt-bindings: clk: meson: add sm1 periph clock controller bindings 
Update the documentation to support clock driver for the Amlogic SM1 SoC
and expose the GP1, DSU and the CPU 1, 2 & 3 clocks.

SM1 clock tree is very close, the main differences are :
- each CPU core can achieve a different frequency, albeit a common PLL
- a similar tree as the clock tree has been added for the DynamIQ Shared
  Unit
- has a new GP1 PLL used for the DynamIQ Shared Unit
- SM1 has additional clocks like for CSI, NanoQ an other components

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2019-08-26 11:00:15 +02:00
Peng Fan
760e548e7f clk: imx: imx8mn: fix audio pll setting 
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
 2019-08-24 21:04:27 +02:00
Jernej Skrabec
65818ad081 clk: sunxi-ng: h6: Allow I2S to change parent rate 
I2S doesn't work if parent rate couldn't be change. Difference between
wanted and actual rate is too big.

Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
 2019-08-21 17:20:31 +08:00
Jerome Brunet
7cfefab656 clk: meson: axg-audio: add g12a reset support 
On the g12a, the register space dedicated to the audio clock also
provides some resets. Let the clock controller register a reset
provider as well for this SoC family.

the axg SoC family does not appear to provide this feature.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2019-08-20 11:51:36 +02:00