Geert Uytterhoeven a4f8a6e60c clk: renesas: r8a779g0: Add watchdog clock
Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Kazuya Mizuguchi.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a012e4449b976efbeaabebb983fa6cfc1b9329d3.1662714852.git.geert+renesas@glider.be
2022-09-18 14:43:51 +02:00
..
2022-03-11 18:22:15 -08:00
2022-08-04 12:12:54 -07:00
2022-03-11 18:22:15 -08:00
2022-03-11 18:22:15 -08:00
2021-11-02 14:28:51 -07:00