167 Commits

Author SHA1 Message Date
Lijo Lazar
54e6065461 drm/amd/pm: Support board calibration on aldebaran
Add support for board power calibration on Aldebaran.
Board calibration is done after DC offset calibration.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-23 10:07:59 -04:00
Tao Zhou
67a1af079b drm/amd/pm: update DRIVER_IF_VERSION for beige_goby
Update the version to 0xD for beige_goby.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-16 13:51:51 -04:00
Xiaomeng Hou
dde5864539 drm/amd/pm: drop smu_v13_0_1.c|h files for yellow carp
Since there's nothing special in smu implementation for yellow carp,
it's better to reuse the common smu_v13_0 interfaces and drop the
specific smu_v13_0_1.c|h files.

v2: remove the duplicate register offset and shift mask header files as
well.

Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-08 17:47:28 -04:00
Evan Quan
a6556ed8ea drm/amd/pm: bump DRIVER_IF_VERSION for Sienna Cichlid
To suppress the annoying warning about version mismatch.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-08 17:47:28 -04:00
Evan Quan
b407a3aa28 drm/amd/pm: new SmuMetrics data structure for Sienna Cichlid
Due to the structure layout change: "uint32_t ThrottlerStatus" -> "
uint8_t  ThrottlingPercentage[THROTTLER_COUNT]".

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-08 17:47:28 -04:00
Alex Deucher
6963d6c176 drm/amdgpu: add a mutex for the smu11 i2c bus (v2)
So we lock software as well as hardware access to the bus.

v2: fix mutex handling.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
2021-07-01 00:24:39 -04:00
Stanley.Yang
513befa634 drm/amdgpu: message smu to update hbm bad page number
Use SMU to update the bad pages rather than directly
accessing the EEPROM from the driver.

Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-18 17:11:56 -04:00
Evan Quan
488f211dab drm/amd/pm: correct the power limits reporting on OOB supported
As OOB(out-of-band) interface may be used to update the power limits.
Thus to make sure the power limits reporting of our driver always
reflects the correct values, the internal cache must be aligned
carefully.

V2: add support for out-of-band of other ASICs
    align cached current power limit with OOB imposed

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-By: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11 16:03:09 -04:00
Evan Quan
1e75be2b67 drm/amd/pm: update the cached dpm feature status
For some ASICs, the real dpm feature disablement job is handled by
PMFW during baco reset and custom pptable loading. Cached dpm feature
status need to be updated to pair that.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11 16:02:30 -04:00
Evan Quan
13d75eadfa drm/amd/pm: correct the runpm handling for BACO supported ASIC
Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the
Dstate change. Driver involvement for determining the timing for
BACO enter/exit is not needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11 16:01:57 -04:00
Graham Sider
1049de4305 drm/amd/pm: Add ASIC independent throttle bits
Add new defines for thermal throttle status bits which are ASIC
independent. This bit field will be visible to userspace via
gpu_metrics alongside the previous ASIC dependent bit fields. Seperated
into four types: power throttlers (16 bits), current throttlers (16
bits), temperature (24 bits), other (8 bits).

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10 11:44:25 -04:00
Darren Powell
4f9cbeb317 amdgpu/pm: modify and add smu_get_power_limit to Powerplay API
modify args of smu_get_power_limit to match Powerplay API .get_power_limit
 add smu_get_power_limit to Powerplay API swsmu_pm_funcs
 remove special handling of smu in amdgpu_hwmon_show_power_cap*

* Test
 AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
 AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
 HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

 lspci -nn | grep "VGA\|Display" ; \
 echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ;           \
 echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ;   \
 echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08 12:13:56 -04:00
Darren Powell
a40a020de2 amdgpu/pm: clean up smu_get_power_limit function signature
add two new powerplay enums (limit_level, type)
 add enums to smu_get_power_limit signature
 remove input bitfield stuffing of output variable limit
 update calls to smu_get_power_limit

* Test
 AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
 AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
 HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

 lspci -nn | grep "VGA\|Display" ; \
 echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ;           \
 echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ;   \
 echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08 12:13:40 -04:00
Xiaomeng Hou
3df43e65e7 drm/amd/pm: add callback to get bootup values for yellow carp
Add get_vbios_bootup_values function to get the bootup values for yellow
carp.

Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 16:03:22 -04:00
Aaron Liu
999dc9c520 drm/amdgpu/pm: add gfx_off_control for yellow carp
This patch implements gfx_off_control.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 16:03:15 -04:00
Aaron Liu
e44510e24e drm/amdgpu/pm: add set_driver_table_location implementation for yellow carp
This patch adds set_driver_table_location implementation for yellow
carp.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 16:03:13 -04:00
Aaron Liu
120a6db472 drm/amdgpu: add smu ip block for yellow carp(V3)
Yellow carp smu ip version: 13_0_1.
V2: rename smu_v13_0 to smu_v13_0_1.
V3: reuse smu_v13_0 with aldebaran.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 16:03:11 -04:00
Aaron Liu
20761d0a79 drm/amd/pm: add smu13 ip support for moment(V3)
For supporting yellow carp, we need to add smu13 ip
support for the moment.

V2: add smu_v13_0_1.c|h dedicated for apu.
V3: cleanup code.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 16:03:10 -04:00
Aaron Liu
e1aeab8a21 drm/amdgpu/pm: add smu v13.0.1 smc header for yellow carp (v2)
This patch is to add smu v13.0.1 smc header for yellow carp.

v2: squash in updates (Alex)

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 16:03:10 -04:00
Aaron Liu
52dfd6c47e drm/amdgpu/pm: add smu v13.0.1 firmware header for yellow carp (V4)
This patch is to add smu v13.0.1 firmware header for yellow carp.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 16:03:09 -04:00
Aaron Liu
385bb92fdc drm/admgpu/pm: add smu v13 driver interface header for yellow carp (v3)
This patch is to add smu v13 driver interface header for yellow carp.

v2: squash in updates (Alex)
v3: squash in v69.29.0 update (Alex)

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 16:03:09 -04:00
Sathishkumar S
a7673a1c1a drm/amd/pm: sysfs attrs to read ss powershare (v6)
add sysfs attrs to read smartshift APU and DGPU power share.
document the sysfs device attributes.

V2: change variable/macro name for stapm power limit (Lijo)
V3: files to be exposed as sysfs device attributes (Alex)
V4: check ret value of sysfs create and remove only if created.
V5: add ss attrs in amdgpu_device_attrs and use attr_update (Lijo)
V6: all checks for ss support to be in if else if statements. (Lijo)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04 12:40:00 -04:00
Lee Jones
d26ebc5852 drm/amd/pm/inc/smu_v13_0: Move table into the only source file that uses it
Fixes the following W=1 kernel build warning(s):

 drivers/gpu/drm/amd/amdgpu/../pm/inc/smu_v13_0.h:54:43: warning: ‘smu13_thermal_policy’ defined but not used [-Wunused-const-variable=]

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: David Airlie <airlied@linux.ie>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Kevin Wang <kevin1.wang@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-27 12:33:50 -04:00
Chengming Gui
c15e2739b8 drm/amd/pm: Correct reserved uint32_t number in beige_goby_PPTable
Correct reserved number according to the latest struct in drm-next

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-21 17:59:36 -04:00
Chengming Gui
9256e54209 drm/amd/pm: Update PPTable struct for beige_goby
Update PPTable structure since SMC#73.9/IFWI-XXX.013

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-21 10:32:03 -04:00
Chengming Gui
fbe8115c6a drm/amd/pm: update smu11 driver interface header for beige_goby
Use new struct name to identify beige_goby pptable
due to extra added fields.

v2: squash in updates (Alex)

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Evan Quan <Evan.Quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-19 22:41:06 -04:00
Chengming Gui
4d3526690a drm/amd/amdgpu: add smu support for beige_goby
Use soft-pptable for beige_goby

v2: fix format

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-19 22:40:44 -04:00
Lijo Lazar
eed13b0e37 drm/amd/pm: Add custom/current freq to pstates
Add custom member for user requested custom frequency, level mask
or min/max frequencies. Add curr member to keep track of the current
active values.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-19 22:38:13 -04:00
Lijo Lazar
6e6fe7c928 drm/amd/pm: Update aldebaran pmfw interface
Update aldebaran driver-PMFW interface to version 0x07

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-19 22:29:35 -04:00
Xiaojian Du
eb607a00d3 drm/amd/pm: add the callback to get the bootup values for renoir
This patch is to add the callback to get the bootup values for renoir.

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-15 16:32:44 -04:00
Xiaojian Du
f4994be248 drm/amd/pm: update the driver interface header for vangogh
This patch is to update the driver interface header for vangogh.
New version driver interface header will support new version pmfw
(from version 4.63.36.00) which uses new smu metrics table.

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-15 16:32:19 -04:00
Evan Quan
2d64d23e95 drm/amd/pm: unify the interface for gfx state setting
No need to have special handling for swSMU supported ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:46:51 -04:00
Evan Quan
d2b0b4832b drm/amd/pm: unify the interface for power gating
No need to have special handling for swSMU supported ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:46:46 -04:00
Evan Quan
2e4b2f7b57 drm/amd/pm: unify the interface for loading SMU microcode
No need to have special handling for swSMU supported ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:46:38 -04:00
Lijo Lazar
c941e9fe9c drm/amd/pm: Add support for reset completion on aldebaran
v1: On aldebaran, after hardware context restore, another handshake
needs to happen with PMFW so that reset recovery is complete from
PMFW side. Treat this as RESET_COMPLETE event for aldebaran.

v2: Cleanup coding style, info logs

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:46:05 -04:00
Lijo Lazar
6d77dd9f75 drm/amd/pm: Add function to wait for smu events
v1: Add function to wait for specific event/states from PMFW

v2: Add mutex lock, simplify sequence

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:46:01 -04:00
Alex Deucher
dd67d7a620 drm/amdgpu/pm: mark pcie link/speed arrays as const
They are read only.

Noticed-by: Dave Airlie <airlied@linux.ie>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:43:31 -04:00
Lijo Lazar
9a8fe5557d drm/amd/pm: Update aldebaran pmfw interface
Update aldebaran PMFW interfaces to version 0x6

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:42:59 -04:00
Evan Quan
181e772f7d drm/amd/pm: drop redundant and unneeded BACO APIs V2
Use other APIs which are with the same functionality but much
more clean.

V2: drop mediate unneeded interface

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:42:50 -04:00
Evan Quan
c6ce68e676 drm/amd/pm: label these APIs used internally as static
Also drop unnecessary header file and declarations.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:42:43 -04:00
Evan Quan
5f400639dd drm/amd/pm: make DAL communicate with SMU through unified interfaces
No need to have special handlings for swSMU supported ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:42:37 -04:00
Evan Quan
1689fca0d6 drm/amd/pm: fix Navi1x runtime resume failure V2
The RLC was put into a wrong state on runtime suspend. Thus the RLC
autoload will fail on the succeeding runtime resume. By adding an
intermediate PPSMC_MSG_PrepareMp1ForUnload(some GC hard reset involved,
designed for PnP), we can bring RLC back into the desired state.

V2: integrate INTERRUPTS_ENABLED flag clearing into current
    mp1 state set routines

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-09 16:37:53 -04:00
Eric Huang
6e58941cff drm/amd/pm: add a new sysfs entry for default power limit
Driver doesn't keep the default bootup power limit and expose it
to user. As requested we add it in driver.

Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23 23:30:55 -04:00
Alex Deucher
60d06906cd drm/amdgpu/powerplay/smu10: add support for gpu busy query (v2)
Was added in newer versions of the firmware.  Add support
for it.

v2: return an error in SMU error, drop needless break.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23 23:27:50 -04:00
shaoyunl
0e92159640 drm/amd/pm: Add LightSBR SMU MSG support
This new MSG provide the interface for driver to enable/disable the Light Secondary Bus Reset
support from SMU. When enabled, SMU will only do minimum NBIO response to the SBR request and
leave the real HW reset to be handled by driver later. When disabled (default state),SMU will
pass the request to PSP for a HW reset

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23 23:25:43 -04:00
Kenneth Feng
bea9cd3f8d drm/amd/pm: add new data in metrics table
Export new data in the metrics table for gfx and memory
utilization counter, and each hbm temperature as well.

v2:
change the metrics table version to v1.1

v3:
fix the coding style
v4:
rebase against latest kernel

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23 23:00:28 -04:00
Lijo Lazar
8a6b6b667c drm/amdgpu/pm: Remove redundant generic message index
Remove SMU_MSG_GfxDriverReset generic index.
Always use SMU_MSG_GfxDeviceDriverReset as the generic index for reset.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23 22:57:32 -04:00
Feifei Xu
5c03e5843e drm/amdgpu:add smu mode1/2 support for aldebaran
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset.
Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions.
Add mode2_reset_is_support() for smu->ppt_funcs.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23 22:54:49 -04:00
Kevin Wang
c05d1c4015 drm/amd/swsmu: add aldebaran smu13 ip support (v3)
Add initial swSMU support.

v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth)
v2: switch to thm/mp v13_0 ip headers (Hawking)
v3: squash in updates (Alex)

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23 22:54:24 -04:00
Kevin Wang
465c437aac drm/amd/swsmu: add aldebaran smu driver if header (v2)
add aldebaran smu13 driver if header

v2: squash in updates

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Kenneth Feng <Kenneth.feng@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-23 22:54:20 -04:00