IF YOU WOULD LIKE TO GET AN ACCOUNT, please write an
email to Administrator. User accounts are meant only to access repo
and report issues and/or generate pull requests.
This is a purpose-specific Git hosting for
BaseALT
projects. Thank you for your understanding!
Только зарегистрированные пользователи имеют доступ к сервису!
Для получения аккаунта, обратитесь к администратору.
Highlights:
----------
- MPU:
- STM32MP13:
- Add and enable LTDC display (rocktech,rk043fn48h)
on stm32mp135f-dk.
- Add firewall bus based on ETZPC firewall controller.
- Add PWR regulator support: Can be only used if the platform is
set as "no-secure" (RCC_SECCFGR cleared) either use SCMI
regulator.
- STMP32MP15:
- Add firewall bus based on ETZPC firewall controller.
- Add heartbeat on stm32mp157c-ed1.
- STM32MP25:
- Add firewall bus based on RIFSC firewall controller.
- Add clock support (RCC) based on SCMI clock protocol for root clocks.
- Add all I2C instances and declare i2c2/i2c8 on stm32mp257f-ev1.
- Add all SPI instances. and declare spi3/spi8 on stm32mp257f-ev1.
-----BEGIN PGP SIGNATURE-----
iQJRBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmYqV7odHGFsZXhhbmRy
ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIWlCBAArsf4o7GwC3K3tBAj
ViR8UzGz3leIa0QHrZHhFvVQGjHllWYxBviDmKGRQwNarRlP6hFx+gHxmjqBxqk3
h45Wpa5zGbZMFYwGgdcJWLhB6aYy+GKOvUNuJDAc640K+uj9UECNIogwj80+2WWK
vRs5FrbgNqaZiGo7wKnJshEAHE+c03UEhj0+KD7JTHhGoXN/kX0nVZOqXQ2tH3+n
WNwk7M0dc3Is0cjDuWBlXzc7mDUj7uYtPU2c7kyleNEd6P7ZZ2nmZMus63jqP4Xt
tV0E5mmPqLGx1ABX1v9GXCYXuPu+YmWNTtm7J1Mea6WA6CoWUhTD+4c4Y6tzi3zo
KORQGviXyycZxKD9WEW9SX9swoJuwaapltzaT1VsbpimYx3AlSs0ZRjW5eQ9P9E3
imMqbPEP6r1Qj4M6JD1G8jaCYagzTk6qWBzPNjc2syX5gPczDQltbwNmYS0kaMyb
WVHh91p639Qlnb8gSwdCxMLI5Ppa0OxQcw4xWWbfjxqVF2PMZYdBvO4jPEafbKTZ
foykD/r+q/k6oKWr4Bfme7of+QiQvehFc7BF5Dt3nwIBHuQKeooueMWJe5EZix9o
6FPTCPw7ktnnujBqfsMGM59h3/VZcuW/wcBEOoYu+pZ0g2OODdzeL5lyIyFvRE69
ICpP4thLnATkS2TaSAS9acCwVpA=
=o2fQ
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmYvXb4ACgkQYKtH/8kJ
Uica3xAAso78p08TkahE5cxTyJP3bC5Seiks4vY3pimMQmsmqlYPb5timtHZdKMN
T28o06lrTPs3+A3H+JBA2N2QmZC8JJiCMq2PAUUEneUiKo7N/QVUmUp+N0aeocez
sbJHK4eJsaK2RFAKb5opBPV5ZjAE3Y35qQa1ogMivWvMs7Qaxk/I++xPSIE+N5hl
9gf2RP6EV06R85Lg4G9yUFDWLHc6UiEulQwujx24faTyYAy6J+5gysO0mxn8HhH5
/wR2RTOg2NfyKlNM+kf1R5hoA3EUo1GH0QLBfblSY5cONzCcOyz9IWxinphHLIYN
GPztcRXFl2rJKGJjjW9cgBkMZb1ifGkq95U06BBFiwCTLdam41F9cg0/U8cZJZfG
CGw4Bv5kbVZzlqDLTKiZH4Qmdecqv0qZkzUsqr0b3tmvy7dtaKHOZ/NyNqWIgEtK
kJtyfRCb+y+LV2uyfAy0I8fwea8tH5z/yxVOR+ny5E3zXHjpjnMRDMevg/Z/eWcX
oHqkeXXpLGM9zm1ab6sEa4HT4gW0AGH4o/kqRagbfj4fVca6ldyFHpmndRSiSY43
1S6aW1kIM22oUoTsOrsz+0dt+XYg5Po1tqZDf2yBj6Wgus5qZLz2FlbfoWdL6NGH
lWHy+WuEu/ZXcbwlRda2v2w0nq2QY1EoQx5Ku3WQCABcf33S8no=
=9M2b
-----END PGP SIGNATURE-----
Merge tag 'stm32-dt-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.10, round 1
Highlights:
----------
- MPU:
- STM32MP13:
- Add and enable LTDC display (rocktech,rk043fn48h)
on stm32mp135f-dk.
- Add firewall bus based on ETZPC firewall controller.
- Add PWR regulator support: Can be only used if the platform is
set as "no-secure" (RCC_SECCFGR cleared) either use SCMI
regulator.
- STMP32MP15:
- Add firewall bus based on ETZPC firewall controller.
- Add heartbeat on stm32mp157c-ed1.
- STM32MP25:
- Add firewall bus based on RIFSC firewall controller.
- Add clock support (RCC) based on SCMI clock protocol for root clocks.
- Add all I2C instances and declare i2c2/i2c8 on stm32mp257f-ev1.
- Add all SPI instances. and declare spi3/spi8 on stm32mp257f-ev1.
* tag 'stm32-dt-for-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (21 commits)
arm64: dts: st: correct masks for GIC PPI interrupts on stm32mp25
arm64: dts: st: add spi3 / spi8 properties on stm32mp257f-ev1
arm64: dts: st: add spi3/spi8 pins for stm32mp25
arm64: dts: st: add all 8 spi nodes on stm32mp251
arm64: dts: st: add i2c2 / i2c8 properties on stm32mp257f-ev1
arm64: dts: st: add i2c2/i2c8 pins for stm32mp25
arm64: dts: st: add all 8 i2c nodes on stm32mp251
arm64: dts: st: add rcc support for STM32MP25
ARM: dts: stm32: enable display support on stm32mp135f-dk board
ARM: dts: stm32: add LTDC pinctrl on STM32MP13x SoC family
ARM: dts: stm32: add LTDC support for STM32MP13x SoC family
dt-bindings: display: simple: allow panel-common properties
ARM: dts: stm32: add PWR regulators support on stm32mp131
media: dt-bindings: add access-controllers to STM32MP25 video codecs
ARM: dts: stm32: add heartbeat led for stm32mp157c-ed1
ARM: dts: stm32: move can3 node from stm32f746 to stm32f769
ARM: dts: stm32: put ETZPC as an access controller for STM32MP13x boards
ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards
ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
...
Link: https://lore.kernel.org/r/2040767c-413e-4447-b354-c44999930e4c@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1. Add FIFO depth to each SPI node so we can avoid matching this through
DTS alias. Difference SPI instances on given SoC have different FIFO
depths.
2. Exynos850: add clock controllers providing clocks to CPUs.
3. Google GS101: few cleanups and add missing serial engine (USI)
interface nodes.
-----BEGIN PGP SIGNATURE-----
iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmYqA4gQHGtyemtAa2Vy
bmVsLm9yZwAKCRDBN2bmhouD1yUJEACEAN4PSt1XsENwwH7wyIXn+Yehx4wszoIC
jXiYotrWC8wcqg5gdcimCIyHGSO/Bg6C1UgvMxmo4QLXJ3NnMRWPENqd+k6sfTcW
LxhzJeLGDSYHI3CArPV/gc9WFnypAuDVHrWLOSxgUbvxuv/8nZe7Xd2cGScz2h9G
JHE6Kfpp08S1NtcaTyUNko8/DU2bl9sKjEVP6sDjqtsZqNv5TMLICbUq6R9HervL
bslHCEfTy12Ov0SLmh+wbPhv/Mh6VWW/PO6hA5cvgwFPo3E+Q2UOz2i7wtI1Wff6
8fBBpDaVuJF9vDgDZKxmATHZJpJNLXyaVUmHgPcM8hQ7Yt8aX7jH/Jymr4VSwgho
a0duE/usSYNn5yfO+5d3UWwUv3BY4g4YX0LPTdONu37+J2JFUi88FjDOWPNc/Uh2
o9zieilx2vrzhU6njizlKF9irWSojEzzZEzbWCAhs2JXBJATiPMYvh/zB08yy1oK
Rm9SaznlOBJwCqG6s3DgYTvgsMRj8YkWyLR0AW//4fKCC57WeyLtgfZDRWK+XYZm
XwAtbrbfMZBLq/kxoc4zOJ/UhySnLvlvuXWjRcJKJPqlQDDEGl31KJIbnYQHFr6U
EZWXcsaCGu2yES55RTCgp+hxJfqmOZhc7DVulQoHu7CvEuRr/XOQ8SCpr3PIFkOc
im01Ydquiw==
=NTPF
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmYvWv8ACgkQYKtH/8kJ
UicYNA//Ynh/68Wg83w0+diMFKbM6a0uznzgyLeo9eIKRB7a90AiKLat2UuLHkZH
GTPmQYJur6hbJ2iVoSUI/AMwVX82PFqXGCbWmgbau3515ICFQlW5aJhy7Zm9Ingo
si9bTC5DSAzKwkCyFpbVC0iO6I0dGKZUoVV4nPgqjd7TQUOUg1kwMFrKcLymPBWv
d9fit6bLZTMBLtZa9+b+DGvpe0Bkv9IVR8PFDYCkcSZg6/JaXrdoKwZ/pTl2DZLG
bifP3v8P9VOGahC29E+oOliAIk3Z5Uey4cwc5tQIZ76G3o0MUqLCngtdW7SngFnx
JcP9MhB9hoQB7zB7Bz8kKeDLKl/Jk7YW83hWqPbdJYSybQdySR28AWMZXGmvMmWe
q8Z5tp6uQMfCPsrBAZmBQJEx/fBGbALlbeuwV7vXHvCXeItlWZ6FsX7coWhz5rNq
Dt8KC9niT7VZGYn3gzaNs9SSMvWj9x7uB4v669k5N6LnyQku3iL+z9RDi/OCVx3X
gJWHKf55KmZicjHSrCaTIADUeblK18dxeKzxVOh3DSM6PVJL4nLTExTA4Zl21gAv
Caxwbl10rrZTrNcVXld1Bm5QWvbYjjIT+I0sAzwMzj/4FbLFdzRparjwCNCccQ6i
DcLZZpKusgFXhW1J/setxITi0pV1PASYX5narCHa+xWfK4sHJ5k=
=K6Ie
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.10
1. Add FIFO depth to each SPI node so we can avoid matching this through
DTS alias. Difference SPI instances on given SoC have different FIFO
depths.
2. Exynos850: add clock controllers providing clocks to CPUs.
3. Google GS101: few cleanups and add missing serial engine (USI)
interface nodes.
* tag 'samsung-dt64-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: gs101: define all PERIC USI nodes
arm64: dts: exynos: gs101: join lines close to 80 chars
arm64: dts: exynos: gs101: move pinctrl-* properties after clocks
arm64: dts: exynos: gs101: move serial_0 pinctrl-0/names to dtsi
arm64: dts: exynos: gs101: reorder pinctrl-* properties
arm64: dts: exynos850: Add CPU clocks
arm64: dts: exynosautov9: specify the SPI FIFO depth
arm64: dts: exynos5433: specify the SPI FIFO depth
Link: https://lore.kernel.org/r/20240425071856.9235-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Update n900 charge limit, and make use of the clksel binding for dra7
for the clksel clocks and other dpll output related clocks.
-----BEGIN PGP SIGNATURE-----
iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAmYp3y0RHHRvbnlAYXRv
bWlkZS5jb20ACgkQG9Q+yVyrpXPjUw/8CEk27NriuwwJ51pnDYL+kVMprTPvTRnn
BPTXHduIIZjoKpSQxBoSx3vu/YklKPzrzng/OjyqLwINH228Edn4zufweuVRmHwa
oXwQvnJyFoeKGjsMbUz57DThFosWUecWMpBUU3n/9/gZC64YAy4P5jXXJkAJXac4
iU4pfdZ3NuNW2Pv+g7DrUatvvqFPx8E2NvonMLVCUuZDxhQXo6XQQMNHrrLySPbq
K45Z2864rj4Td2/T3X3GUVXbKI5xOZ63M2sVtYP5Z0UVBs+Ay3Rvj1YcELOWfPMi
17fzPd7sJ+wCPDFohF8UlpNEOns5m1KdTf1gRgPfB8vwQ/KghtOU7s+cTgeTJan3
nb1PuMcetRhJpAqmWPYhWPLRBNDjZEadp6pjNRRbABzO4uC1W4RhmrQ5lG5CBsHD
SUF+snnLnQmmH7K3c+gtyyt/+Is0Ga2bq82Z/n4LvGsPk6pZScnMtxZJVEfJiknC
ZEEA3t1F5HhzQaZaTx401Kwijj1oEg+54axjiL0ze9JLSL7NUMphCz6IJVKPOyNo
WzH37RmwM/mFNAXbX317sJXERYdjY6wRY7lRPkLF19NP4CQkJ5/ckcYum4J8PmX9
RRpEhnMWl2Fsb7LmPYLH3/rIAUsa0aQ1jgY/wr4oVdHxs/Lf008Lc5S4zCklPAeV
PXWGGMTLmxc=
=+DGK
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmYvWmwACgkQYKtH/8kJ
Uic36w/+IKBMt8RR+lKWfY2Pn4QMjx4BgM68FoZ8fnC8BvX8jOaE66RpaxdZm/oC
UAFsUPr/R232bBn4VzpjlsCUot0DoyEfucFO/Tvav9CukCL9bafMMYQ48fOpdK/h
wYFBbohCDtdVIpqmXgEPcgyoC2WlyYlF19diM2OeFUidk/Yp/q6XTu8o5wxZ4I6i
zM81BfN4zmnfogAr9N1Wkf8j3DQN1fXyHKVRHc5wRerMB0Y9jzggjdY0gSePvp2A
Pc+BhXR17nSt+hnvuqR+ACIx1LPmO72O89RqIzthoEBhZwrboJNOCjR7+JF71kv+
On3dWm6rIkE9H+qj1fnVKD4H+QI9kIT6pijzBc3myH1LFsG6HL/ZUZjre1gY+XiX
3bfiwSBV495akdMToJdBy0sRezZJdfbAIpTurCJoDaTg8M7f8nCROVrftHXEPDDn
RxT5USrW56/MsRoHT4gAxGDch8IWqmddgQ4v9sXa5QzomPPznLK9g3FRfdKrklbS
OwHzX7nk7TeqHUrAIEcXeq0JcR5/4aTTg824dbg1D1EM8J8zwdMHE1nus6jLOpz9
XcoX6AqScW6xlBMZMmXpkSE0iE1kyCVuaDSgX4JXIfsAHKUsqOWzUSSOkntoTby+
rhDa5ofDrwhU/DvOyL/aIRH3+wErF6ZMNe4FmAr0Pcu2YA8JTEM=
=jNDn
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt
Devicetree changes for omaps for v6.10
Update n900 charge limit, and make use of the clksel binding for dra7
for the clksel clocks and other dpll output related clocks.
* tag 'omap-for-v6.10/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: dra7: Use clksel binding for CTRL_CORE_SMA_SW_0
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_USB
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_PER
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_ABE_PLL_SYS
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_CORE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_EVE
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GMAC
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DRR
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_GPU
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_IVA
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_DSP
ARM: dts: dra7: Use clksel binding for CM_CLKSEL_DPLL_CORE
ARM: dts: n900: set charge current limit to 950mA
Link: https://lore.kernel.org/r/pull-1714020191-304166@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily,
it doesn't provide any detail on uarch specific events.
There's still remaining cases for CPUs without any corresponding PMU
definition and for big.LITTLE systems which only have a single PMU node
(there should be one per core type).
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Bjorn Andersson <andersson@kernel.org>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Acked-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Link: https://lore.kernel.org/r/20240417203853.3212103-1-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add HDMI capture support for the Function expansion board for the
Eagle development board,
- Add PMIC support for the RZ/G2UL SMARC EVK development board,
- Add thermal, more serial ((H)SCIF), and timer (CMT and TMU) support
for the R-Car V4M SoC,
- Add Timer Unit (TMU) support for the R-Mobile APE6, R-Car Gen2, and
RZ/G1 SoCs,
- Miscellaneous fixes and improvements.
-----BEGIN PGP SIGNATURE-----
iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCZhkAtwAKCRCKwlD9ZEnx
cI/UAQDXti0XEMAK5NpdccmUjvlm4TYxTkoV7RB+bkfR+i4fgwEA3O6jjBa0y8fO
kH98OKMQpukHOm0Y4NwWPbQXB2rOKgM=
=eCJv
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmYvWKcACgkQYKtH/8kJ
UiewCg/9FQ3syL/oB0w7LnCJrqUXk5v+BpwSZqEGWmwjcsO27RkDe18kmeROPkK4
1rJpkx4rjkMbqHQd63bFj5nUF9j5G4Rd8z/BXQKFKlh1O79lZNZmFqOny/u4L4d4
8vUF4qvbhKel0ffzSspJ4tiaySDkQP41OKCpGDXPiy2vzl0UHY4cohg4Qvdrs4kO
L/JgtIrr4sBWBq7rFDn4NUG/0QQfx8Uqgt4m6HXZjOc4CaHrh/MjnI7FULQ5EqAv
d9+sbNjTfvQ5W4pklEL+s/bspe0+KdVetj5dy0GVpwxQA6YKnabpnMNzzOB2k25Q
lpSKt8dpQJi07YiHoR8q72V5vzwc63kvQQc/uC/feQ/QC94HDFCqe4ZeGPWTcZOj
ChE2YA4+2zXIQj+1wIRies3EMgWUamcdzVgG9JxZGKAnofoo/kaEkkPo+mgBFkF9
xaQvtVNbuUlyuCYt/FDisBIAgEJjIwxtG568pZl/sbMuEAb0NLCTprepEMJbH6Dr
F1o0LHGu8VQJtFWvwkfyp/n9DB14b0kZTmtGlF2bZE31FiVR+scDvUurh3Oh4lWB
R4UnAQUXGhSoJhtJJ7WFB/nv26JFouvafiM3Vt3bm5VncxbYgku4/9wzeJv1PDG9
/o9yXIH405jdhd4D72qVGmrCbqr0d7qkJgc7mdQAKsjQVhoe/as=
=7aeg
-----END PGP SIGNATURE-----
Merge tag 'renesas-dts-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.10
- Add HDMI capture support for the Function expansion board for the
Eagle development board,
- Add PMIC support for the RZ/G2UL SMARC EVK development board,
- Add thermal, more serial ((H)SCIF), and timer (CMT and TMU) support
for the R-Car V4M SoC,
- Add Timer Unit (TMU) support for the R-Mobile APE6, R-Car Gen2, and
RZ/G1 SoCs,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: rzg3s-smarc-som: Fix Ethernet aliases
arm64: dts: renesas: r8a779h0: Add TMU nodes
arm64: dts: renesas: r8a779h0: Add CMT nodes
arm64: dts: renesas: gray-hawk-single: Enable nfsroot
ARM: dts: renesas: r9a06g032: Remove duplicate interrupt-parent
arm64: dts: renesas: gray-hawk-single: Add second debug serial port
arm64: dts: renesas: r8a779h0: Add SCIF nodes
arm64: dts: renesas: r8a779h0: Add remaining HSCIF nodes
ARM: dts: renesas: rcar-gen2: Add TMU nodes
ARM: dts: renesas: rzg1: Add TMU nodes
ARM: dts: renesas: r8a73a4: Add TMU nodes
ARM: dts: renesas: r7s72100: Add interrupt-names to SCIF nodes
arm64: dts: renesas: r8a779h0: Add thermal nodes
arm64: dts: renesas: rzg2ul-smarc: Enable PMIC and built-in RTC, GPIO and ONKEY
arm64: dts: renesas: eagle: Add capture overlay for Function expansion board
Link: https://lore.kernel.org/r/cover.1712915536.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs.
STM32MP251 is a single core Cortex A35, STM32MP253 is a dual core CA35.
Fixes: 5d30d03aaf78 ("arm64: dts: st: introduce stm32mp25 SoCs family")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add properties for spi3 and spi8 available on the stm32mp257f-ev1.
Both are kept disabled since only used via the gpio expansion connector.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add the spi3 and spi8 pins used on STM32MP257F-EV1 board.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add the 8 nodes for all spi instances available on the stm32mp251.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add properties for i2c2 and i2c8 available on the stm32mp257f-ev1.
i2c2 is enabled since several devices are attached to it while
i2c8 is kept disabled since only used via the gpio expansion connector.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add the i2c2 and i2c8 pins used on STM32MP257F-EV1 board.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add the 8 nodes for all i2c instances available on the stm32mp251.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Add RCC support to manage clocks and resets on the STM32MP25.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
STM32MP13x SoC family embeds a new version of LTDC (Liquid crystal
display - Thin film transistor) Display Controller.
It provides a parallel digital RGB (red, green, blue) and signals for
horizontal, vertical synchronization, pixel clock and data enable as
output to interface directly to a variety of LCD-TFT panels.
Main features
* 2 input layers blended together to compose the display
* Cropping of layers from any input size and location
* Multiple input pixel formats:
– Predefined ARGB, with 7 formats: ARGB8888, ABGR8888, RGBA8888,
BGRA8888, RGB565, BGR565, RGB888packed.
– Flexible ARGB, allowing any width and location for A,R,G,B
components.
– Predefined YUV, with 3 formats: YUV422-1L (FourCC: YUYV,
Interleaved), YUV420-2L (FourCC: NV12, semi planar), YUV420-3L
(FourCC: Yxx, full planar) with some flexibility on the sequence of
the component.
* Color look-up table (CLUT) up to 256 colors (256x24 bits) per layer
* Color transparency keying
* Composition with flexible window position and size versus output
display
* Blending with flexible layer order and alpha value (per pixel or
constant)
* Background underlying color
* Gamma with non-linear configurable table
* Dithering for output with less bits per component (pseudo-random on
2 bits)
* Polarity inversion for HSync, VSync, and DataEnable outputs
* Output as RGB888 24 bpp or YUV422 16 bpp
* Secure layer (using Layer2) capability, with grouped regs and
additional interrupt set
* Interrupts based on 7 different events
* AXI master interface with long efficient bursts (64 or 128 bytes)
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This device inherits properties from panel-common. Those should be allowed
to use, instead of specifying properties to true for each specific use.
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This patch adds STM32 PWR regulators DT support on stm32mp131.
This requires TFA to clear RCC_SECCFGR, is disabled by default
and can only be enabled on board DT level.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
access-controllers is an optional property that allows a peripheral to
refer to one or more domain access controller(s).
Signed-off-by: Hugues Fruchet <hugues.fruchet@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
According to documents [1], [2] and [3], we have 2 CAN devices on the
stm32f746 platform and 3 on the stm32f769 platform. So let's move the
can3 node from stm32f746.dtsi to stm32f769.dtsi.
[1] https://www.st.com/en/microcontrollers-microprocessors/stm32f7-series.html
[2] RM0385: STM32F75xxx and STM32F74xxx advanced Arm®-based 32-bit MCUs
[3] RM0410: STM32F76xxx and STM32F77xxx advanced Arm®-based 32-bit MCUs
Fixes: df362914eead ("ARM: dts: stm32: re-add CAN support on stm32f746")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reference ETZPC as an access-control-provider.
For more information on which peripheral is securable or supports MCU
isolation, please read the STM32MP13 reference manual
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
ETZPC is a firewall controller. Put all peripherals filtered by the
ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for
backward compatibility.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reference ETZPC as an access-control-provider.
For more information on which peripheral is securable or supports MCU
isolation, please read the STM32MP15 reference manual
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
ETZPC is a firewall controller. Put all peripherals filtered by the
ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for
backward compatibility.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Fixed regulators are not part of any MMIO bus, so they should not have
unit addresses. This fixes dtc W=1 warnings:
hi6220-hikey.dts:85.26-92.4: Warning (unit_address_vs_reg): /regulator@0: node has a unit name, but no reg or ranges property
hi6220-hikey.dts:94.27-102.4: Warning (unit_address_vs_reg): /regulator@1: node has a unit name, but no reg or ranges property
hi6220-hikey.dts:104.26-113.4: Warning (unit_address_vs_reg): /regulator@2: node has a unit name, but no reg or ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
adv7533 ports should have "reg" propeties, as reported by dtc W=1
warnings:
hi6220-hikey.dts:516.11-520.6: Warning (unit_address_vs_reg): /soc/i2c@f7102000/adv7533@39/ports/port@0: node has a unit name, but no reg or ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Non-MMIO devices, which are BTW not really part of the SoC, should not
be within simple-bus, as reported by dtc W=1 warning:
hip07.dtsi:1486.20-1493.5: Warning (unit_address_vs_reg): /soc/ethernet@4: node has a unit name, but no reg or ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Correct dsa and pcie unit addresses to fix dtc W=1 warnings:
hip06.dtsi:439.23-571.5: Warning (simple_bus_reg): /soc/dsa@c7000000: simple-bus unit address format error, expected "c5000000"
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Non-MMIO devices, which are BTW not really part of the SoC, should not
be within simple-bus, as reported by dtc W=1 warning:
hip06.dtsi:377.18-381.5: Warning (simple_bus_reg): /soc/refclk: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Correct local-bus children unit addresses to fix dtc W=1 warnings:
hip05-d02.dts:57.16-76.4: Warning (simple_bus_reg): /soc/local-bus@80380000/nor-flash@0,0: simple-bus unit address format error, expected "0"
hip05-d02.dts:78.11-81.4: Warning (simple_bus_reg): /soc/local-bus@80380000/cpld@1,0: simple-bus unit address format error, expected "100000000"
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Non-MMIO devices, which are BTW not really part of the SoC, should not
be within simple-bus, as reported by dtc W=1 warning:
hip05.dtsi:301.30-305.5: Warning (simple_bus_reg): /soc/refclk200mhz: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
On dra76x, most dpll_gmac output clksel clocks are in registers from
CM_CLKSEL_DPLL_GMAC to CM_DIV_H13_DPLL_GMAC. In addition to that, there
are there more clocks in the CTRL_CORE_SMA_SW_0 register.
Let's group the CTRL_CORE_SMA_SW_0 clocks using the clksel binding to
reduce make W=1 dtbs unique_unit_address warnings, and stop using the
custom the ti,bit-shift property in favor of the standard reg property.
Let's also add a comment for the CTRL_CORE_SMA_SW_0 clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
With the clkcsel binding we can drop the custom ti,bit-shift devicetree
property in favor of the standard reg property and reduce the number of
clocks to update for the make W-1 dtbs warnings.
Let's also add a comment for the clocksel clock that matches the
documentation.
Signed-off-by: Tony Lindgren <tony@atomide.com>
